diff -pruN 1:3.6.2-3/bindings/ocaml/executionengine/llvm_executionengine.ml 1:3.6.2-4/bindings/ocaml/executionengine/llvm_executionengine.ml --- 1:3.6.2-3/bindings/ocaml/executionengine/llvm_executionengine.ml 2014-12-24 01:52:51.000000000 +0000 +++ 1:3.6.2-4/bindings/ocaml/executionengine/llvm_executionengine.ml 2016-10-07 23:09:53.000000000 +0000 @@ -43,11 +43,11 @@ external run_static_dtors : llexecutione = "llvm_ee_run_static_dtors" external data_layout : llexecutionengine -> Llvm_target.DataLayout.t = "llvm_ee_get_data_layout" -external add_global_mapping_ : Llvm.llvalue -> int64 -> llexecutionengine -> unit +external add_global_mapping_ : Llvm.llvalue -> nativeint -> llexecutionengine -> unit = "llvm_ee_add_global_mapping" -external get_global_value_address_ : string -> llexecutionengine -> int64 +external get_global_value_address_ : string -> llexecutionengine -> nativeint = "llvm_ee_get_global_value_address" -external get_function_address_ : string -> llexecutionengine -> int64 +external get_function_address_ : string -> llexecutionengine -> nativeint = "llvm_ee_get_function_address" let add_global_mapping llval ptr ee = @@ -55,14 +55,14 @@ let add_global_mapping llval ptr ee = let get_global_value_address name typ ee = let vptr = get_global_value_address_ name ee in - if Int64.to_int vptr <> 0 then + if Nativeint.to_int vptr <> 0 then let open Ctypes in !@ (coerce (ptr void) (ptr typ) (ptr_of_raw_address vptr)) else raise (Error ("Value " ^ name ^ " not found")) let get_function_address name typ ee = let fptr = get_function_address_ name ee in - if Int64.to_int fptr <> 0 then + if Nativeint.to_int fptr <> 0 then let open Ctypes in coerce (ptr void) typ (ptr_of_raw_address fptr) else raise (Error ("Function " ^ name ^ " not found")) diff -pruN 1:3.6.2-3/debian/changelog 1:3.6.2-4/debian/changelog --- 1:3.6.2-3/debian/changelog 2015-10-20 16:41:19.000000000 +0000 +++ 1:3.6.2-4/debian/changelog 2016-10-07 18:18:00.000000000 +0000 @@ -1,3 +1,23 @@ +llvm-toolchain-3.6 (1:3.6.2-4) unstable; urgency=medium + + * Team upload + + [ Gianfranco Costamagna ] + * Import some changes from Ubuntu. + * Fix powerpc sadness by not using gold linker. + + [ Matthias Klose ] + * d/p/rL235088.diff: + - [AArch64] Fix invalid use of references to BuildMI, taken from the trunk. + * d/p/no-version-script-for-executables.diff: + - Do not link executables with a version script. + + [ Louis Bouchard ] + * d/rules: Fix the regex for the GCC_VERSION so it takes version 6 + into account. Otherwise, this causes an FTBS (Closes: #835582) + + -- Gianfranco Costamagna Fri, 07 Oct 2016 08:21:03 +0200 + llvm-toolchain-3.6 (1:3.6.2-3) unstable; urgency=medium * Add a Break/Replaces clang-3.6 (<< 1:3.6.2-2) from clang-tidy-3.6 diff -pruN 1:3.6.2-3/debian/llvm-X.Y.links.in 1:3.6.2-4/debian/llvm-X.Y.links.in --- 1:3.6.2-3/debian/llvm-X.Y.links.in 2015-01-14 18:45:58.000000000 +0000 +++ 1:3.6.2-4/debian/llvm-X.Y.links.in 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -# AUTOGENERATED in debian/rules.d/binary.mk. diff -pruN 1:3.6.2-3/debian/llvm-X.Y-runtime.links.in 1:3.6.2-4/debian/llvm-X.Y-runtime.links.in --- 1:3.6.2-3/debian/llvm-X.Y-runtime.links.in 2015-01-14 18:45:58.000000000 +0000 +++ 1:3.6.2-4/debian/llvm-X.Y-runtime.links.in 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -# AUTOGENERATED in debian/rules.d/binary.mk. diff -pruN 1:3.6.2-3/debian/patches/llvm-3.6.0-ocaml-ctypes-0.4.0.patch 1:3.6.2-4/debian/patches/llvm-3.6.0-ocaml-ctypes-0.4.0.patch --- 1:3.6.2-3/debian/patches/llvm-3.6.0-ocaml-ctypes-0.4.0.patch 1970-01-01 00:00:00.000000000 +0000 +++ 1:3.6.2-4/debian/patches/llvm-3.6.0-ocaml-ctypes-0.4.0.patch 2016-10-07 06:17:49.000000000 +0000 @@ -0,0 +1,35 @@ +diff -Naur llvm-3.6.0.src.orig/bindings/ocaml/executionengine/llvm_executionengine.ml llvm-3.6.0.src/bindings/ocaml/executionengine/llvm_executionengine.ml +--- llvm-3.6.0.src.orig/bindings/ocaml/executionengine/llvm_executionengine.ml 2015-03-17 11:49:27.274824345 +0100 ++++ llvm-3.6.0.src/bindings/ocaml/executionengine/llvm_executionengine.ml 2015-03-17 11:49:40.333829421 +0100 +@@ -43,11 +43,11 @@ + = "llvm_ee_run_static_dtors" + external data_layout : llexecutionengine -> Llvm_target.DataLayout.t + = "llvm_ee_get_data_layout" +-external add_global_mapping_ : Llvm.llvalue -> int64 -> llexecutionengine -> unit ++external add_global_mapping_ : Llvm.llvalue -> nativeint -> llexecutionengine -> unit + = "llvm_ee_add_global_mapping" +-external get_global_value_address_ : string -> llexecutionengine -> int64 ++external get_global_value_address_ : string -> llexecutionengine -> nativeint + = "llvm_ee_get_global_value_address" +-external get_function_address_ : string -> llexecutionengine -> int64 ++external get_function_address_ : string -> llexecutionengine -> nativeint + = "llvm_ee_get_function_address" + + let add_global_mapping llval ptr ee = +@@ -55,14 +55,14 @@ + + let get_global_value_address name typ ee = + let vptr = get_global_value_address_ name ee in +- if Int64.to_int vptr <> 0 then ++ if Nativeint.to_int vptr <> 0 then + let open Ctypes in !@ (coerce (ptr void) (ptr typ) (ptr_of_raw_address vptr)) + else + raise (Error ("Value " ^ name ^ " not found")) + + let get_function_address name typ ee = + let fptr = get_function_address_ name ee in +- if Int64.to_int fptr <> 0 then ++ if Nativeint.to_int fptr <> 0 then + let open Ctypes in coerce (ptr void) typ (ptr_of_raw_address fptr) + else + raise (Error ("Function " ^ name ^ " not found")) diff -pruN 1:3.6.2-3/debian/patches/no-version-script-for-executables.diff 1:3.6.2-4/debian/patches/no-version-script-for-executables.diff --- 1:3.6.2-3/debian/patches/no-version-script-for-executables.diff 1970-01-01 00:00:00.000000000 +0000 +++ 1:3.6.2-4/debian/patches/no-version-script-for-executables.diff 2016-10-07 06:17:53.000000000 +0000 @@ -0,0 +1,28 @@ +Index: b/Makefile.rules +=================================================================== +--- a/Makefile.rules ++++ b/Makefile.rules +@@ -1411,12 +1411,13 @@ else + $(ToolBuildPath): $(ToolDir)/.dir + endif + ++COMMA = , + ifdef CODESIGN_TOOLS + TOOL_CODESIGN_IDENTITY ?= - + + $(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) + $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) +- $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ ++ $(Verb) $(filter-out -Wl$(COMMA)--version-script=%,$(Link)) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) + $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ + $(StripWarnMsg) +@@ -1425,7 +1426,7 @@ $(ToolBuildPath): $(ObjectsO) $(ProjLibs + else + $(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) + $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) +- $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ ++ $(Verb) $(filter-out -Wl$(COMMA)--version-script=%,$(Link)) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) + $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ + $(StripWarnMsg) diff -pruN 1:3.6.2-3/debian/patches/rL235088.diff 1:3.6.2-4/debian/patches/rL235088.diff --- 1:3.6.2-3/debian/patches/rL235088.diff 1970-01-01 00:00:00.000000000 +0000 +++ 1:3.6.2-4/debian/patches/rL235088.diff 2016-10-07 06:17:53.000000000 +0000 @@ -0,0 +1,31 @@ +Index: b/lib/Target/AArch64/AArch64InstrInfo.cpp +=================================================================== +--- a/lib/Target/AArch64/AArch64InstrInfo.cpp ++++ b/lib/Target/AArch64/AArch64InstrInfo.cpp +@@ -1527,7 +1527,7 @@ void AArch64InstrInfo::copyPhysRegTuple( + } + + for (; SubReg != End; SubReg += Incr) { +- const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode)); ++ const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode)); + AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); + AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI); + AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); +@@ -1905,7 +1905,7 @@ void AArch64InstrInfo::storeRegToStackSl + } + assert(Opc && "Unknown register class"); + +- const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc)) ++ const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI); + +@@ -2003,7 +2003,7 @@ void AArch64InstrInfo::loadRegFromStackS + } + assert(Opc && "Unknown register class"); + +- const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc)) ++ const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) + .addReg(DestReg, getDefRegState(true)) + .addFrameIndex(FI); + if (Offset) diff -pruN 1:3.6.2-3/debian/patches/series 1:3.6.2-4/debian/patches/series --- 1:3.6.2-3/debian/patches/series 2015-09-21 09:14:07.000000000 +0000 +++ 1:3.6.2-4/debian/patches/series 2016-10-07 06:18:14.000000000 +0000 @@ -38,3 +38,6 @@ clang-analyzer-force-version.diff bug783205.patch bug-24472.diff bug-790686-build-id.diff +llvm-3.6.0-ocaml-ctypes-0.4.0.patch +rL235088.diff +no-version-script-for-executables.diff diff -pruN 1:3.6.2-3/debian/rules 1:3.6.2-4/debian/rules --- 1:3.6.2-3/debian/rules 2015-10-20 16:40:08.000000000 +0000 +++ 1:3.6.2-4/debian/rules 2016-10-07 18:15:51.000000000 +0000 @@ -3,9 +3,9 @@ TARGET_BUILD := build-llvm DEB_INST := $(CURDIR)/debian/tmp/ #GCC_VERSION := 4.8 -# The 5| in the regexp is a crappy workaround. g++ 5.2 in Debian is not providing a g++-5.2 binary (only g++-5) +# The 5|6| in the regexp is a crappy workaround. g++ 5.2 in Debian is not providing a g++-5.2 binary (only g++-5) # accomodate that by hardcoding the 5 detection -GCC_VERSION := $(shell dpkg-query -W -f '$${Version}' g++ | sed -rne 's,^([0-9]+:)?(5|[0-9]+\.[0-9]+|[0-9]+).*$$,\2,p') +GCC_VERSION := $(shell dpkg-query -W -f '$${Version}' g++ | sed -rne 's,^([0-9]+:)?(5|6|[0-9]+\.[0-9]+|[0-9]+).*$$,\2,p') LLVM_VERSION := 3.6 LLVM_VERSION_FULL := $(LLVM_VERSION).2 SONAME_EXT := 1 @@ -62,9 +62,9 @@ else control_vars = '-Vdep:devlibs=libstdc++6-$(GCC_VERSION)-dev' endif -BINUTILS_GOLD_ARCHS := amd64 armhf i386 powerpc powerpcspe ppc64 ppc64el sparc sparc64 x32 +BINUTILS_GOLD_ARCHS := amd64 armhf i386 powerpcspe ppc64 ppc64el sparc sparc64 x32 ifeq ($(shell dpkg --compare-versions $(shell dpkg-query -W -f '$${Version}' binutils) ge 2.23.1-1~exp3 ; echo $$?),0) -ifneq (,$(findstring $(DEB_HOST_ARCH),$(BINUTILS_GOLD_ARCHS))) +ifneq (,$(filter $(DEB_HOST_ARCH),$(BINUTILS_GOLD_ARCHS))) # -fused-ld=gold enables the gold linker (but is not supported by all archs / distro) LDFLAGS_EXTRA += -fuse-ld=gold endif @@ -212,12 +212,11 @@ override_dh_auto_configure: preconfigure --with-cloog --with-isl \ --with-bug-report-url=http://bugs.debian.org/ \ --enable-shared \ - --disable-bindings \ + --disable-bindings \ $(CONFIGURE_EXTRA) \ CLANG_VENDOR=$(VENDOR) || { cat config.log tools/polly/config.log; exit 1; } # cd $(TARGET_BUILD) && cmake ../ -DCMAKE_INSTALL_PREFIX=/usr -DCMAKE_VERBOSE_MAKEFILE=ON # mkdir build-compiler-rt && cd build-compiler-rt && cmake ../compiler-rt -# --with-ocaml-libdir=/usr/lib/ocaml/llvm-$(LLVM_VERSION) \ override_dh_auto_build: diff -pruN 1:3.6.2-3/lib/Target/AArch64/AArch64InstrInfo.cpp 1:3.6.2-4/lib/Target/AArch64/AArch64InstrInfo.cpp --- 1:3.6.2-3/lib/Target/AArch64/AArch64InstrInfo.cpp 2015-01-14 11:23:27.000000000 +0000 +++ 1:3.6.2-4/lib/Target/AArch64/AArch64InstrInfo.cpp 2016-10-07 23:09:53.000000000 +0000 @@ -1527,7 +1527,7 @@ void AArch64InstrInfo::copyPhysRegTuple( } for (; SubReg != End; SubReg += Incr) { - const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode)); + const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode)); AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI); AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); @@ -1905,7 +1905,7 @@ void AArch64InstrInfo::storeRegToStackSl } assert(Opc && "Unknown register class"); - const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc)) + const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI); @@ -2003,7 +2003,7 @@ void AArch64InstrInfo::loadRegFromStackS } assert(Opc && "Unknown register class"); - const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc)) + const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) .addReg(DestReg, getDefRegState(true)) .addFrameIndex(FI); if (Offset) diff -pruN 1:3.6.2-3/Makefile.rules 1:3.6.2-4/Makefile.rules --- 1:3.6.2-3/Makefile.rules 2014-11-05 00:35:15.000000000 +0000 +++ 1:3.6.2-4/Makefile.rules 2016-10-07 23:09:53.000000000 +0000 @@ -1411,12 +1411,13 @@ else $(ToolBuildPath): $(ToolDir)/.dir endif +COMMA = , ifdef CODESIGN_TOOLS TOOL_CODESIGN_IDENTITY ?= - $(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) - $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(Verb) $(filter-out -Wl$(COMMA)--version-script=%,$(Link)) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ $(StripWarnMsg) @@ -1425,7 +1426,7 @@ $(ToolBuildPath): $(ObjectsO) $(ProjLibs else $(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) - $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(Verb) $(filter-out -Wl$(COMMA)--version-script=%,$(Link)) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ $(StripWarnMsg) diff -pruN 1:3.6.2-3/.pc/applied-patches 1:3.6.2-4/.pc/applied-patches --- 1:3.6.2-3/.pc/applied-patches 2016-10-07 23:09:45.452406384 +0000 +++ 1:3.6.2-4/.pc/applied-patches 2016-10-07 23:09:53.908639538 +0000 @@ -37,3 +37,6 @@ clang-analyzer-force-version.diff bug783205.patch bug-24472.diff bug-790686-build-id.diff +llvm-3.6.0-ocaml-ctypes-0.4.0.patch +rL235088.diff +no-version-script-for-executables.diff diff -pruN 1:3.6.2-3/.pc/llvm-3.6.0-ocaml-ctypes-0.4.0.patch/bindings/ocaml/executionengine/llvm_executionengine.ml 1:3.6.2-4/.pc/llvm-3.6.0-ocaml-ctypes-0.4.0.patch/bindings/ocaml/executionengine/llvm_executionengine.ml --- 1:3.6.2-3/.pc/llvm-3.6.0-ocaml-ctypes-0.4.0.patch/bindings/ocaml/executionengine/llvm_executionengine.ml 1970-01-01 00:00:00.000000000 +0000 +++ 1:3.6.2-4/.pc/llvm-3.6.0-ocaml-ctypes-0.4.0.patch/bindings/ocaml/executionengine/llvm_executionengine.ml 2014-12-24 01:52:51.000000000 +0000 @@ -0,0 +1,72 @@ +(*===-- llvm_executionengine.ml - LLVM OCaml Interface --------*- OCaml -*-===* + * + * The LLVM Compiler Infrastructure + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + * + *===----------------------------------------------------------------------===*) + +exception Error of string + +let () = Callback.register_exception "Llvm_executionengine.Error" (Error "") + +external initialize : unit -> bool + = "llvm_ee_initialize" + +type llexecutionengine + +type llcompileroptions = { + opt_level: int; + code_model: Llvm_target.CodeModel.t; + no_framepointer_elim: bool; + enable_fast_isel: bool; +} + +let default_compiler_options = { + opt_level = 0; + code_model = Llvm_target.CodeModel.JITDefault; + no_framepointer_elim = false; + enable_fast_isel = false } + +external create : ?options:llcompileroptions -> Llvm.llmodule -> llexecutionengine + = "llvm_ee_create" +external dispose : llexecutionengine -> unit + = "llvm_ee_dispose" +external add_module : Llvm.llmodule -> llexecutionengine -> unit + = "llvm_ee_add_module" +external remove_module : Llvm.llmodule -> llexecutionengine -> unit + = "llvm_ee_remove_module" +external run_static_ctors : llexecutionengine -> unit + = "llvm_ee_run_static_ctors" +external run_static_dtors : llexecutionengine -> unit + = "llvm_ee_run_static_dtors" +external data_layout : llexecutionengine -> Llvm_target.DataLayout.t + = "llvm_ee_get_data_layout" +external add_global_mapping_ : Llvm.llvalue -> int64 -> llexecutionengine -> unit + = "llvm_ee_add_global_mapping" +external get_global_value_address_ : string -> llexecutionengine -> int64 + = "llvm_ee_get_global_value_address" +external get_function_address_ : string -> llexecutionengine -> int64 + = "llvm_ee_get_function_address" + +let add_global_mapping llval ptr ee = + add_global_mapping_ llval (Ctypes.raw_address_of_ptr (Ctypes.to_voidp ptr)) ee + +let get_global_value_address name typ ee = + let vptr = get_global_value_address_ name ee in + if Int64.to_int vptr <> 0 then + let open Ctypes in !@ (coerce (ptr void) (ptr typ) (ptr_of_raw_address vptr)) + else + raise (Error ("Value " ^ name ^ " not found")) + +let get_function_address name typ ee = + let fptr = get_function_address_ name ee in + if Int64.to_int fptr <> 0 then + let open Ctypes in coerce (ptr void) typ (ptr_of_raw_address fptr) + else + raise (Error ("Function " ^ name ^ " not found")) + +(* The following are not bound. Patches are welcome. +target_machine : llexecutionengine -> Llvm_target.TargetMachine.t + *) diff -pruN 1:3.6.2-3/.pc/no-version-script-for-executables.diff/Makefile.rules 1:3.6.2-4/.pc/no-version-script-for-executables.diff/Makefile.rules --- 1:3.6.2-3/.pc/no-version-script-for-executables.diff/Makefile.rules 1970-01-01 00:00:00.000000000 +0000 +++ 1:3.6.2-4/.pc/no-version-script-for-executables.diff/Makefile.rules 2014-11-05 00:35:15.000000000 +0000 @@ -0,0 +1,2164 @@ +#===-- Makefile.rules - Common make rules for LLVM ---------*- Makefile -*--===# +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +#===------------------------------------------------------------------------===# +# +# This file is included by all of the LLVM makefiles. For details on how to use +# it properly, please see the document MakefileGuide.html in the docs directory. +# +#===-----------------------------------------------------------------------====# + +################################################################################ +# TARGETS: Define standard targets that can be invoked +################################################################################ + +#-------------------------------------------------------------------- +# Define the various target sets +#-------------------------------------------------------------------- +RecursiveTargets := all clean clean-all install uninstall install-bytecode \ + unitcheck +LocalTargets := all-local clean-local clean-all-local check-local \ + install-local printvars uninstall-local \ + install-bytecode-local +TopLevelTargets := check dist dist-check dist-clean dist-gzip dist-bzip2 \ + dist-zip unittests +UserTargets := $(RecursiveTargets) $(LocalTargets) $(TopLevelTargets) +InternalTargets := preconditions distdir dist-hook + +################################################################################ +# INITIALIZATION: Basic things the makefile needs +################################################################################ + +#-------------------------------------------------------------------- +# Set the VPATH so that we can find source files. +#-------------------------------------------------------------------- +VPATH=$(PROJ_SRC_DIR) + +#-------------------------------------------------------------------- +# Reset the list of suffixes we know how to build. +#-------------------------------------------------------------------- +.SUFFIXES: +.SUFFIXES: .c .cpp .cc .h .hpp .o .a .td .ps .dot .m .mm +.SUFFIXES: $(SHLIBEXT) $(SUFFIXES) + +#-------------------------------------------------------------------- +# Mark all of these targets as phony to avoid implicit rule search +#-------------------------------------------------------------------- +.PHONY: $(UserTargets) $(InternalTargets) + +#-------------------------------------------------------------------- +# Make sure all the user-target rules are double colon rules and +# they are defined first. +#-------------------------------------------------------------------- + +$(UserTargets):: + +#------------------------------------------------------------------------ +# LLVMBuild Integration +#------------------------------------------------------------------------ +# +# We use llvm-build to generate all the data required by the Makefile based +# build system in one swoop: +# +# - We generate a file (a Makefile fragment) in the object root which contains +# all the definitions that are required by Makefiles across the entire +# project. +# +# - We generate the library table used by llvm-config. +# +# - We generate the dependencies for the Makefile fragment, so that we will +# automatically reconfigure outselves. + +# The path to the llvm-build tool itself. +LLVMBuildTool := $(PROJ_SRC_ROOT)/utils/llvm-build/llvm-build + +# The files we are going to generate using llvm-build. +LLVMBuildMakeFrag := $(PROJ_OBJ_ROOT)/Makefile.llvmbuild +LLVMBuildCMakeFrag := $(PROJ_OBJ_ROOT)/LLVMBuild.cmake +LLVMBuildCMakeExportsFrag := $(PROJ_OBJ_ROOT)/cmake/modules/LLVMBuildExports.cmake +LLVMBuildMakeFrags := \ + $(LLVMBuildMakeFrag) \ + $(LLVMBuildCMakeFrag) \ + $(LLVMBuildCMakeExportsFrag) +LLVMConfigLibraryDependenciesInc := \ + $(PROJ_OBJ_ROOT)/tools/llvm-config/LibraryDependencies.inc + +# This is for temporary backwards compatibility. +ifndef TARGET_NATIVE_ARCH +TARGET_NATIVE_ARCH := $(ARCH) +endif + +# The rule to create the LLVMBuild Makefile fragment as well as the llvm-config +# library table. +# +# Note that this target gets its real dependencies generated for us by +# llvm-build. +# +# We include a dependency on this Makefile to ensure that changes to the +# generation command get picked up. +$(LLVMBuildMakeFrags): $(PROJ_SRC_ROOT)/Makefile.rules \ + $(PROJ_OBJ_ROOT)/Makefile.config + $(Echo) Constructing LLVMBuild project information. + $(Verb)$(PYTHON) $(LLVMBuildTool) \ + --native-target "$(TARGET_NATIVE_ARCH)" \ + --enable-targets "$(TARGETS_TO_BUILD)" \ + --enable-optional-components "$(OPTIONAL_COMPONENTS)" \ + --write-library-table $(LLVMConfigLibraryDependenciesInc) \ + --write-make-fragment $(LLVMBuildMakeFrag) \ + --write-cmake-fragment $(LLVMBuildCMakeFrag) \ + --write-cmake-exports-fragment $(LLVMBuildCMakeExportsFrag) + +# For completeness, let Make know how the extra files are generated. +$(LLVMConfigLibraryDependenciesInc): $(LLVMBuildMakeFrags) + +# Include the generated Makefile fragment. +# +# We currently only include the dependencies for the fragment itself if we are +# at the top-level. Otherwise, recursive invocations would ends up doing +# substantially more redundant stat'ing. +# +# This means that we won't properly regenerate things for developers used to +# building from a subdirectory, but that is always somewhat unreliable. +ifeq ($(LEVEL),.) +LLVMBUILD_INCLUDE_DEPENDENCIES := 1 + +# Clean the generated makefile fragment at the top-level. +clean-local:: + -$(Verb) $(RM) -f $(LLVMBuildMakeFrags) +endif +-include $(LLVMBuildMakeFrag) + +################################################################################ +# PRECONDITIONS: that which must be built/checked first +################################################################################ + +SrcMakefiles := $(filter %Makefile %Makefile.tests,\ + $(wildcard $(PROJ_SRC_DIR)/Makefile*)) +ObjMakefiles := $(subst $(PROJ_SRC_DIR),$(PROJ_OBJ_DIR),$(SrcMakefiles)) +ConfigureScript := $(PROJ_SRC_ROOT)/configure +ConfigStatusScript := $(PROJ_OBJ_ROOT)/config.status +MakefileConfigIn := $(strip $(wildcard $(PROJ_SRC_ROOT)/Makefile.config.in)) +MakefileCommonIn := $(strip $(wildcard $(PROJ_SRC_ROOT)/Makefile.common.in)) +MakefileConfig := $(PROJ_OBJ_ROOT)/Makefile.config +MakefileCommon := $(PROJ_OBJ_ROOT)/Makefile.common +PreConditions := $(ConfigStatusScript) $(ObjMakefiles) +ifneq ($(MakefileCommonIn),) +PreConditions += $(MakefileCommon) +endif + +ifneq ($(MakefileConfigIn),) +PreConditions += $(MakefileConfig) +endif + +preconditions: $(PreConditions) + +#------------------------------------------------------------------------ +# Make sure the BUILT_SOURCES are built first +#------------------------------------------------------------------------ +$(filter-out clean clean-local,$(UserTargets)):: $(BUILT_SOURCES) + +clean-all-local:: +ifneq ($(strip $(BUILT_SOURCES)),) + -$(Verb) $(RM) -f $(BUILT_SOURCES) +endif + +ifneq ($(PROJ_OBJ_ROOT),$(PROJ_SRC_ROOT)) +spotless: + $(Verb) if test -x config.status ; then \ + $(EchoCmd) Wiping out $(PROJ_OBJ_ROOT) ; \ + $(MKDIR) .spotless.save ; \ + $(MV) config.status .spotless.save ; \ + $(MV) mklib .spotless.save ; \ + $(MV) projects .spotless.save ; \ + $(RM) -rf * ; \ + $(MV) .spotless.save/config.status . ; \ + $(MV) .spotless.save/mklib . ; \ + $(MV) .spotless.save/projects . ; \ + $(RM) -rf .spotless.save ; \ + $(EchoCmd) Rebuilding configuration of $(PROJ_OBJ_ROOT) ; \ + $(ConfigStatusScript) --recheck $(ConfigureScriptFLAGS) && \ + $(ConfigStatusScript) ; \ + else \ + $(EchoCmd) "make spotless" can only be run from $(PROJ_OBJ_ROOT); \ + fi +else +spotless: + $(EchoCmd) "spotless target not supported for objdir == srcdir" +endif + +$(BUILT_SOURCES) : $(ObjMakefiles) + +#------------------------------------------------------------------------ +# Make sure we're not using a stale configuration +#------------------------------------------------------------------------ +reconfigure: + $(Echo) Reconfiguring $(PROJ_OBJ_ROOT) + $(Verb) cd $(PROJ_OBJ_ROOT) && \ + $(ConfigStatusScript) --recheck $(ConfigureScriptFLAGS) && \ + $(ConfigStatusScript) + +.PRECIOUS: $(ConfigStatusScript) +$(ConfigStatusScript): $(ConfigureScript) + $(Echo) Reconfiguring with $< + $(Verb) cd $(PROJ_OBJ_ROOT) && \ + $(ConfigStatusScript) --recheck $(ConfigureScriptFLAGS) && \ + $(ConfigStatusScript) + +#------------------------------------------------------------------------ +# Make sure the configuration makefile is up to date +#------------------------------------------------------------------------ +ifneq ($(MakefileConfigIn),) +$(MakefileConfig): $(MakefileConfigIn) $(ConfigStatusScript) + $(Echo) Regenerating $@ + $(Verb) cd $(PROJ_OBJ_ROOT) ; $(ConfigStatusScript) Makefile.config +endif + +ifneq ($(MakefileCommonIn),) +$(MakefileCommon): $(MakefileCommonIn) $(ConfigStatusScript) + $(Echo) Regenerating $@ + $(Verb) cd $(PROJ_OBJ_ROOT) ; $(ConfigStatusScript) Makefile.common +endif + +#------------------------------------------------------------------------ +# If the Makefile in the source tree has been updated, copy it over into the +# build tree. But, only do this if the source and object makefiles differ +#------------------------------------------------------------------------ +ifndef PROJ_MAKEFILE +PROJ_MAKEFILE := $(PROJ_SRC_DIR)/Makefile +endif + +ifneq ($(PROJ_OBJ_DIR),$(PROJ_SRC_DIR)) + +Makefile: $(PROJ_MAKEFILE) $(ExtraMakefiles) + $(Echo) "Updating Makefile" + $(Verb) $(MKDIR) $(@D) + $(Verb) $(CP) -f $< $@ + +# Copy the Makefile.* files unless we're in the root directory which avoids +# the copying of Makefile.config.in or other things that should be explicitly +# taken care of. +$(PROJ_OBJ_DIR)/Makefile% : $(PROJ_MAKEFILE)% + @case '$?' in \ + *Makefile.rules) ;; \ + *.in) ;; \ + *) $(EchoCmd) "Updating $(@F)" ; \ + $(MKDIR) $(@D) ; \ + $(CP) -f $< $@ ;; \ + esac + +endif + +#------------------------------------------------------------------------ +# Set up the basic dependencies +#------------------------------------------------------------------------ +$(UserTargets):: $(PreConditions) + +all:: all-local +clean:: clean-local +clean-all:: clean-local clean-all-local +install:: install-local +uninstall:: uninstall-local +install-local:: all-local +install-bytecode:: install-bytecode-local + +############################################################################### +# VARIABLES: Set up various variables based on configuration data +############################################################################### + +# Variable for if this make is for a "cleaning" target +ifneq ($(strip $(filter clean clean-local dist-clean,$(MAKECMDGOALS))),) + IS_CLEANING_TARGET=1 +endif + +#-------------------------------------------------------------------- +# Variables derived from configuration we are building +#-------------------------------------------------------------------- + +CPP.Defines := +ifeq ($(ENABLE_OPTIMIZED),1) + BuildMode := Release + # Don't use -fomit-frame-pointer on Darwin or FreeBSD. + ifneq ($(HOST_OS), $(filter $(HOST_OS), Cygwin Darwin DragonFly FreeBSD GNU/kFreeBSD)) + OmitFramePointer := -fomit-frame-pointer + endif + + CXX.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer) + C.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer) + LD.Flags += $(OPTIMIZE_OPTION) + ifdef DEBUG_SYMBOLS + BuildMode := $(BuildMode)+Debug + CXX.Flags += -g + C.Flags += -g + KEEP_SYMBOLS := 1 + endif +else + ifdef NO_DEBUG_SYMBOLS + BuildMode := Unoptimized + CXX.Flags += + C.Flags += + KEEP_SYMBOLS := 1 + else + BuildMode := Debug + ifeq ($(ENABLE_SPLIT_DWARF), 1) + CXX.Flags += -gsplit-dwarf + C.Flags += -gsplit-dwarf + else + CXX.Flags += -g + C.Flags += -g + endif + KEEP_SYMBOLS := 1 + endif +endif + +ifeq ($(ENABLE_LIBCPP),1) + CXX.Flags += -stdlib=libc++ + LD.Flags += -stdlib=libc++ +endif + +ifeq ($(ENABLE_CXX1Y),1) + CXX.Flags += -std=c++1y +else + ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) + # MinGW and Cygwin are a bit stricter and lack things like + # 'strdup', 'stricmp', etc in c++11 mode. + CXX.Flags += -std=gnu++11 + else + CXX.Flags += -std=c++11 + endif +endif + +ifeq ($(ENABLE_WERROR),1) + CXX.Flags += -Werror + C.Flags += -Werror +endif + +ifeq ($(ENABLE_PROFILING),1) + BuildMode := $(BuildMode)+Profile + CXX.Flags := $(filter-out -fomit-frame-pointer,$(CXX.Flags)) -pg -g + C.Flags := $(filter-out -fomit-frame-pointer,$(C.Flags)) -pg -g + LD.Flags := $(filter-out -fomit-frame-pointer,$(LD.Flags)) -pg + KEEP_SYMBOLS := 1 +endif + +ifeq ($(ENABLE_VISIBILITY_INLINES_HIDDEN),1) + CXX.Flags += -fvisibility-inlines-hidden +endif + +ifdef ENABLE_EXPENSIVE_CHECKS + # GNU libstdc++ uses RTTI if you define _GLIBCXX_DEBUG, which we did above. + # See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40160 + REQUIRES_RTTI := 1 +endif + +# IF REQUIRES_EH=1 is specified then don't disable exceptions +ifndef REQUIRES_EH + CXX.Flags += -fno-exceptions +else + # If the library requires EH, it also requires RTTI. + REQUIRES_RTTI := 1 +endif + +ifdef REQUIRES_FRAME_POINTER + CXX.Flags := $(filter-out -fomit-frame-pointer,$(CXX.Flags)) + C.Flags := $(filter-out -fomit-frame-pointer,$(C.Flags)) + LD.Flags := $(filter-out -fomit-frame-pointer,$(LD.Flags)) +endif + +# If REQUIRES_RTTI=1 is specified then don't disable run-time type id. +ifneq ($(REQUIRES_RTTI), 1) + CXX.Flags += -fno-rtti +endif + +ifeq ($(ENABLE_COVERAGE),1) + BuildMode := $(BuildMode)+Coverage + CXX.Flags += -ftest-coverage -fprofile-arcs + C.Flags += -ftest-coverage -fprofile-arcs + LD.Flags += -ftest-coverage -fprofile-arcs +endif + +# If DISABLE_ASSERTIONS=1 is specified (make command line or configured), +# then disable assertions by defining the appropriate preprocessor symbols. +ifeq ($(DISABLE_ASSERTIONS),1) + CPP.Defines += -DNDEBUG +else + BuildMode := $(BuildMode)+Asserts + CPP.Defines += -D_DEBUG +endif + +# If ENABLE_EXPENSIVE_CHECKS=1 is specified (make command line or +# configured), then enable expensive checks by defining the +# appropriate preprocessor symbols. +ifeq ($(ENABLE_EXPENSIVE_CHECKS),1) + BuildMode := $(BuildMode)+Checks + CPP.Defines += -D_GLIBCXX_DEBUG -DXDEBUG +endif + +# LOADABLE_MODULE implies several other things so we force them to be +# defined/on. +ifdef LOADABLE_MODULE + SHARED_LIBRARY := 1 + LINK_LIBS_IN_SHARED := 1 +endif + +ifdef SHARED_LIBRARY + ENABLE_PIC := 1 + PIC_FLAG = "(PIC)" +endif + +ifeq ($(ENABLE_PIC),1) + ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) + # Nothing. Win32 defaults to PIC and warns when given -fPIC + else + ifeq ($(HOST_OS),Darwin) + # Common symbols not allowed in dylib files + CXX.Flags += -fno-common + C.Flags += -fno-common + else + # Linux and others; pass -fPIC + CXX.Flags += -fPIC + C.Flags += -fPIC + endif + endif +else + ifeq ($(HOST_OS),Darwin) + CXX.Flags += -mdynamic-no-pic + C.Flags += -mdynamic-no-pic + endif +endif + +# Support makefile variable to disable any kind of timestamp/non-deterministic +# info from being used in the build. +ifeq ($(ENABLE_TIMESTAMPS),1) + DOTDIR_TIMESTAMP_COMMAND := $(DATE) +else + DOTDIR_TIMESTAMP_COMMAND := echo 'Created.' +endif + +ifeq ($(HOST_OS),MingW) + # Work around PR4957 + CPP.Defines += -D__NO_CTYPE_INLINE + ifeq ($(LLVM_CROSS_COMPILING),1) + # Work around http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=525016 + ifdef TOOLNAME + LD.Flags += -Wl,--allow-multiple-definition + endif + endif +endif + +CPP.BaseFlags += $(CPP.Defines) +AR.Flags := cru + +# Make Floating point IEEE compliant on Alpha. +ifeq ($(ARCH),Alpha) + CXX.Flags += -mieee + CPP.BaseFlags += -mieee +ifeq ($(ENABLE_PIC),0) + CXX.Flags += -fPIC + CPP.BaseFlags += -fPIC +endif + + LD.Flags += -Wl,--no-relax +endif + +# GNU ld/PECOFF accepts but ignores them below; +# --version-script +# --export-dynamic +# --rpath +# FIXME: autoconf should be aware of them. +ifneq (,$(filter $(HOST_OS),Cygwin MingW)) + HAVE_LINK_VERSION_SCRIPT := 0 + RPATH := + RDYNAMIC := -Wl,--export-all-symbols +endif + +#-------------------------------------------------------------------- +# Directory locations +#-------------------------------------------------------------------- +TargetMode := +ifeq ($(LLVM_CROSS_COMPILING),1) + BuildLLVMToolDir := $(LLVM_OBJ_ROOT)/BuildTools/$(BuildMode)/bin +endif + +ObjRootDir := $(PROJ_OBJ_DIR)/$(BuildMode) +ObjDir := $(ObjRootDir) +LibDir := $(PROJ_OBJ_ROOT)/$(BuildMode)/lib +ToolDir := $(PROJ_OBJ_ROOT)/$(BuildMode)/bin +ExmplDir := $(PROJ_OBJ_ROOT)/$(BuildMode)/examples +LLVMLibDir := $(LLVM_OBJ_ROOT)/$(BuildMode)/lib +LLVMToolDir := $(LLVM_OBJ_ROOT)/$(BuildMode)/bin +LLVMExmplDir:= $(LLVM_OBJ_ROOT)/$(BuildMode)/examples + +#-------------------------------------------------------------------- +# Locations of shared libraries +#-------------------------------------------------------------------- + +SharedPrefix := lib +SharedLibDir := $(LibDir) +LLVMSharedLibDir := $(LLVMLibDir) + +# Win32.DLL prefers to be located on the "PATH" of binaries. +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) + SharedLibDir := $(ToolDir) + LLVMSharedLibDir := $(LLVMToolDir) + + ifeq ($(HOST_OS),Cygwin) + SharedPrefix := cyg + else + SharedPrefix := + endif +endif + +#-------------------------------------------------------------------- +# Full Paths To Compiled Tools and Utilities +#-------------------------------------------------------------------- +EchoCmd := $(ECHO) llvm[$(MAKELEVEL)]: +ifdef BUILD_DIRS_ONLY +EchoCmd := $(EchoCmd) "(build tools)": +endif + +Echo := @$(EchoCmd) +ifndef LLVMAS +LLVMAS := $(LLVMToolDir)/llvm-as$(EXEEXT) +endif +ifndef LLVM_TBLGEN + ifeq ($(LLVM_CROSS_COMPILING),1) + LLVM_TBLGEN := $(BuildLLVMToolDir)/llvm-tblgen$(BUILD_EXEEXT) + else + LLVM_TBLGEN := $(LLVMToolDir)/llvm-tblgen$(EXEEXT) + endif +endif +ifeq ($(LLVM_CROSS_COMPILING),1) + LLVM_CONFIG := $(BuildLLVMToolDir)/llvm-config$(BUILD_EXEEXT) +else + LLVM_CONFIG := $(LLVMToolDir)/llvm-config$(EXEEXT) +endif +ifndef LLVMDIS +LLVMDIS := $(LLVMToolDir)/llvm-dis$(EXEEXT) +endif +ifndef LLI +LLI := $(LLVMToolDir)/lli$(EXEEXT) +endif +ifndef LLC +LLC := $(LLVMToolDir)/llc$(EXEEXT) +endif +ifndef LOPT +LOPT := $(LLVMToolDir)/opt$(EXEEXT) +endif +ifndef LBUGPOINT +LBUGPOINT := $(LLVMToolDir)/bugpoint$(EXEEXT) +endif +ifndef LLVMLINK +LLVMLINK := $(LLVMToolDir)/llvm-link$(EXEEXT) +endif + +#-------------------------------------------------------------------- +# Adjust to user's request +#-------------------------------------------------------------------- + +ifeq ($(HOST_OS),Darwin) + ifdef MACOSX_DEPLOYMENT_TARGET + DARWIN_VERSION := $(MACOSX_DEPLOYMENT_TARGET) + else + DARWIN_VERSION := `sw_vers -productVersion` + endif + # Strip a number like 10.4.7 to 10.4 + DARWIN_VERSION := $(shell echo $(DARWIN_VERSION)| sed -E 's/(10.[0-9]+).*/\1/') + # Get "4" out of 10.4 for later pieces in the makefile. + DARWIN_MAJVERS := $(shell echo $(DARWIN_VERSION)| sed -E 's/10.([0-9]+).*/\1/') + + LoadableModuleOptions := -Wl,-flat_namespace -Wl,-undefined,suppress + SharedLinkOptions := -dynamiclib + ifdef DEPLOYMENT_TARGET + SharedLinkOptions += $(DEPLOYMENT_TARGET) + else + ifneq ($(ARCH),ARM) + SharedLinkOptions += -mmacosx-version-min=$(DARWIN_VERSION) + endif + endif +else + SharedLinkOptions=-shared +endif + +ifeq ($(TARGET_OS),Darwin) + ifdef DEPLOYMENT_TARGET + TargetCommonOpts += $(DEPLOYMENT_TARGET) + else + ifneq ($(ARCH),ARM) + TargetCommonOpts += -mmacosx-version-min=$(DARWIN_VERSION) + endif + endif +endif + +ifdef SHARED_LIBRARY +ifneq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +ifneq ($(HOST_OS),Darwin) + LD.Flags += $(RPATH) -Wl,'$$ORIGIN' +else + LD.Flags += -Wl,-install_name -Wl,"@rpath/lib$(LIBRARYNAME)$(SHLIBEXT)" +endif +endif +endif + +ifdef TOOL_VERBOSE + C.Flags += -v + CXX.Flags += -v + LD.Flags += -v + VERBOSE := 1 +endif + +# Adjust settings for verbose mode +ifndef VERBOSE + Verb := @ + AR.Flags += >/dev/null 2>/dev/null + ConfigureScriptFLAGS += >$(PROJ_OBJ_DIR)/configure.out 2>&1 +else + ConfigureScriptFLAGS := +endif + +# By default, strip symbol information from executable +ifndef KEEP_SYMBOLS + Strip := $(PLATFORMSTRIPOPTS) + StripWarnMsg := "(without symbols)" + Install.StripFlag += -s +endif + +# By default, strip dead symbols at link time +ifneq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +ifneq ($(HOST_OS),Darwin) +ifneq ($(HOST_ARCH),Mips) + CXX.Flags += -ffunction-sections -fdata-sections +endif +endif +endif +ifndef NO_DEAD_STRIP + ifeq ($(HOST_OS),Darwin) + LD.Flags += -Wl,-dead_strip + else + ifneq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) + LD.Flags += -Wl,--gc-sections + endif + endif +endif + +# Adjust linker flags for building an executable +ifneq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) + ifndef TOOL_NO_EXPORTS + LD.Flags += $(RDYNAMIC) + endif + ifneq ($(HOST_OS), Darwin) + ifdef TOOLNAME + LD.Flags += $(RPATH) -Wl,'$$ORIGIN/../lib' + endif + else + ifneq ($(DARWIN_MAJVERS),4) + LD.Flags += $(RPATH) -Wl,@executable_path/../lib + endif + ifeq ($(RC_XBS),YES) + TempFile := $(shell mkdir -p ${OBJROOT}/dSYMs ; mktemp ${OBJROOT}/dSYMs/llvm-lto.XXXXXX) + LD.Flags += -Wl,-object_path_lto -Wl,$(TempFile) + endif + endif +endif + + +#---------------------------------------------------------- +# Options To Invoke Tools +#---------------------------------------------------------- + +ifdef EXTRA_LD_OPTIONS +LD.Flags += $(EXTRA_LD_OPTIONS) +endif + +ifndef NO_PEDANTIC +CompileCommonOpts += -pedantic -Wno-long-long +endif +CompileCommonOpts += -Wall -W -Wno-unused-parameter -Wwrite-strings \ + $(EXTRA_OPTIONS) $(COVERED_SWITCH_DEFAULT) \ + $(NO_UNINITIALIZED) $(NO_MAYBE_UNINITIALIZED) \ + $(NO_MISSING_FIELD_INITIALIZERS) $(NO_COMMENT) +# Enable cast-qual for C++; the workaround is to use const_cast. +CXX.Flags += -Wcast-qual + +ifeq ($(HOST_OS),HP-UX) + CompileCommonOpts := -D_REENTRANT -D_HPUX_SOURCE +endif + +# If we are building a universal binary on Mac OS X, pass extra options. This +# is useful to people that want to link the LLVM libraries into their universal +# apps. +# +# The following can be optionally specified: +# UNIVERSAL_SDK_PATH variable can be specified as a path to the SDK to use. +# For Mac OS X 10.4 Intel machines, the traditional one is: +# UNIVERSAL_SDK_PATH=/Developer/SDKs/MacOSX10.4u.sdk/ +# UNIVERSAL_ARCH can be optionally specified to be a list of architectures +# to build for, e.g. UNIVERSAL_ARCH="i386 ppc ppc64". This defaults to +# i386/ppc only. +ifdef UNIVERSAL + ifndef UNIVERSAL_ARCH + UNIVERSAL_ARCH := i386 ppc + endif + UNIVERSAL_ARCH_OPTIONS := $(UNIVERSAL_ARCH:%=-arch %) + TargetCommonOpts += $(UNIVERSAL_ARCH_OPTIONS) + ifdef UNIVERSAL_SDK_PATH + TargetCommonOpts += -isysroot $(UNIVERSAL_SDK_PATH) + endif + + # Building universal cannot compute dependencies automatically. + DISABLE_AUTO_DEPENDENCIES=1 +else + ifeq ($(TARGET_OS),Darwin) + ifeq ($(ARCH),x86_64) + TargetCommonOpts = -m64 + else + ifeq ($(ARCH),x86) + TargetCommonOpts = -m32 + endif + endif + endif +endif + +ifeq ($(HOST_OS),SunOS) +CPP.BaseFlags += -include llvm/Support/Solaris.h +endif + +# On Windows, SharedLibDir != LibDir. The order is important. +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) + LD.Flags += -L$(SharedLibDir) -L$(LibDir) -L$(LLVMToolDir) -L$(LLVMLibDir) +else + LD.Flags += -L$(LibDir) -L$(LLVMLibDir) +endif + +CPP.BaseFlags += -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS +# All -I flags should go here, so that they don't confuse llvm-config. +CPP.Flags += $(sort -I$(PROJ_OBJ_DIR) -I$(PROJ_SRC_DIR) \ + $(patsubst %,-I%/include,\ + $(PROJ_OBJ_ROOT) $(PROJ_SRC_ROOT) \ + $(LLVM_OBJ_ROOT) $(LLVM_SRC_ROOT))) \ + $(CPP.BaseFlags) + +ifeq ($(INCLUDE_BUILD_DIR),1) + CPP.Flags += -I$(ObjDir) +endif + +# SHOW_DIAGNOSTICS support. +ifeq ($(SHOW_DIAGNOSTICS),1) + Compile.Wrapper := env CC_LOG_DIAGNOSTICS=1 \ + CC_LOG_DIAGNOSTICS_FILE="$(LLVM_OBJ_ROOT)/$(BuildMode)/diags" +else + Compile.Wrapper := +endif + +Compile.C = $(Compile.Wrapper) \ + $(CC) $(CPP.Flags) $(C.Flags) $(CFLAGS) $(CPPFLAGS) \ + $(TargetCommonOpts) $(CompileCommonOpts) -c +Compile.CXX = $(Compile.Wrapper) \ + $(CXX) $(CPP.Flags) $(CXX.Flags) $(CXXFLAGS) $(CPPFLAGS) \ + $(TargetCommonOpts) $(CompileCommonOpts) -c +Preprocess.CXX= $(Compile.Wrapper) \ + $(CXX) $(CPP.Flags) $(TargetCommonOpts) $(CPPFLAGS) \ + $(CompileCommonOpts) $(CXX.Flags) -E +Link = $(Compile.Wrapper) \ + $(CXX) $(CXXFLAGS) $(LD.Flags) $(LDFLAGS) \ + $(TargetCommonOpts) $(Strip) + +Preprocess.C = $(CC) $(CPP.Flags) $(C.Flags) $(CPPFLAGS) \ + $(TargetCommonOpts) $(CompileCommonOpts) -E + +ProgInstall = $(INSTALL) $(Install.StripFlag) -m 0755 +ScriptInstall = $(INSTALL) -m 0755 +DataInstall = $(INSTALL) -m 0644 + +# When compiling under Mingw/Cygwin, the tblgen tool expects Windows +# paths. In this case, the SYSPATH function (defined in +# Makefile.config) transforms Unix paths into Windows paths. +TableGen.Flags= -I $(call SYSPATH, $(PROJ_SRC_DIR)) \ + -I $(call SYSPATH, $(LLVM_SRC_ROOT)/include) \ + -I $(call SYSPATH, $(PROJ_SRC_ROOT)/include) \ + -I $(call SYSPATH, $(PROJ_SRC_ROOT)/lib/Target) +LLVMTableGen = $(LLVM_TBLGEN) $(TableGen.Flags) + +Archive = $(AR) $(AR.Flags) +ifdef RANLIB +Ranlib = $(RANLIB) +else +Ranlib = ranlib +endif + +AliasTool = ln -sf + +#---------------------------------------------------------- +# Get the list of source files and compute object file +# names from them. +#---------------------------------------------------------- + +ifndef SOURCES + Sources := $(notdir $(wildcard $(PROJ_SRC_DIR)/*.cpp \ + $(PROJ_SRC_DIR)/*.cc $(PROJ_SRC_DIR)/*.c)) +else + Sources := $(SOURCES) +endif + +ifdef BUILT_SOURCES +Sources += $(filter %.cpp %.c %.cc,$(BUILT_SOURCES)) +endif + +BaseNameSources := $(sort $(basename $(Sources))) +SourceDirs := $(sort $(dir $(Sources))) + +ObjectsO := $(BaseNameSources:%=$(ObjDir)/%.o) +ObjectDirs := $(SourceDirs:%=$(ObjDir)/%) + +#---------------------------------------------------------- +# For Mingw MSYS bash and Python/w32: +# +# $(ECHOPATH) prints DOSish pathstring. +# ex) $(ECHOPATH) /include/sys/types.h +# --> C:/mingw/include/sys/types.h +# built-in "echo" does not transform path to DOSish path. +# +# FIXME: It would not be needed when MSYS's python +# were provided. +#---------------------------------------------------------- + +ifeq (-mingw32,$(findstring -mingw32,$(BUILD_TRIPLE))) + ECHOPATH := $(Verb)$(PYTHON) -u -c "import sys;print ' '.join(sys.argv[1:])" +else + ECHOPATH := $(Verb)$(ECHO) +endif + +############################################################################### +# DIRECTORIES: Handle recursive descent of directory structure +############################################################################### + +#--------------------------------------------------------- +# Provide rules to make install dirs. This must be early +# in the file so they get built before dependencies +#--------------------------------------------------------- + +$(DESTDIR)$(PROJ_bindir) $(DESTDIR)$(PROJ_libdir) $(DESTDIR)$(PROJ_includedir) $(DESTDIR)$(PROJ_etcdir):: + $(Verb) $(MKDIR) $@ + +# To create other directories, as needed, and timestamp their creation +%/.dir: + $(Verb) $(MKDIR) $* > /dev/null + $(Verb) $(DOTDIR_TIMESTAMP_COMMAND) > $@ + +.PRECIOUS: $(LibDir)/.dir $(ToolDir)/.dir $(ExmplDir)/.dir +.PRECIOUS: $(LLVMLibDir)/.dir $(LLVMToolDir)/.dir $(LLVMExmplDir)/.dir + +#--------------------------------------------------------- +# Collect the object directories (as there may be more +# than one if the source code is spread across +# subdirectories). +#--------------------------------------------------------- + +OBJECT_DIRS := $(ObjDir)/.dir $(ObjectDirs:%=%/.dir) +.PRECIOUS: $(OBJECT_DIRS) + +#--------------------------------------------------------- +# Handle the DIRS options for sequential construction +#--------------------------------------------------------- + +SubDirs := +ifdef DIRS +SubDirs += $(DIRS) + +ifneq ($(PROJ_SRC_ROOT),$(PROJ_OBJ_ROOT)) +$(RecursiveTargets):: + $(Verb) for dir in $(DIRS); do \ + if ([ ! -f $$dir/Makefile ] || \ + command test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ + $(MKDIR) $$dir; \ + $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ + fi; \ + ($(MAKE) -C $$dir $@ ) || exit 1; \ + done +else +$(RecursiveTargets):: + $(Verb) for dir in $(DIRS); do \ + ($(MAKE) -C $$dir $@ ) || exit 1; \ + done +endif + +endif + +#--------------------------------------------------------- +# Handle the EXPERIMENTAL_DIRS options ensuring success +# after each directory is built. +#--------------------------------------------------------- +ifdef EXPERIMENTAL_DIRS +$(RecursiveTargets):: + $(Verb) for dir in $(EXPERIMENTAL_DIRS); do \ + if ([ ! -f $$dir/Makefile ] || \ + command test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ + $(MKDIR) $$dir; \ + $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ + fi; \ + ($(MAKE) -C $$dir $@ ) || exit 0; \ + done +endif + +#----------------------------------------------------------- +# Handle the OPTIONAL_PARALLEL_DIRS options for optional parallel construction +#----------------------------------------------------------- +ifdef OPTIONAL_PARALLEL_DIRS + PARALLEL_DIRS += $(foreach T,$(OPTIONAL_PARALLEL_DIRS),$(shell test -d $(PROJ_SRC_DIR)/$(T) -o -f $(T)/Makefile && echo "$(T)")) +endif + +#----------------------------------------------------------- +# Handle the PARALLEL_DIRS options for parallel construction +#----------------------------------------------------------- +ifdef PARALLEL_DIRS + +SubDirs += $(PARALLEL_DIRS) + +# Unfortunately, this list must be maintained if new recursive targets are added +all :: $(addsuffix /.makeall ,$(PARALLEL_DIRS)) +clean :: $(addsuffix /.makeclean ,$(PARALLEL_DIRS)) +clean-all:: $(addsuffix /.makeclean-all,$(PARALLEL_DIRS)) +install :: $(addsuffix /.makeinstall ,$(PARALLEL_DIRS)) +uninstall:: $(addsuffix /.makeuninstall,$(PARALLEL_DIRS)) +install-bytecode :: $(addsuffix /.makeinstall-bytecode,$(PARALLEL_DIRS)) +unitcheck:: $(addsuffix /.makeunitcheck,$(PARALLEL_DIRS)) + +ParallelTargets := $(foreach T,$(RecursiveTargets),%/.make$(T)) + +$(ParallelTargets) : + $(Verb) \ + SD=$(PROJ_SRC_DIR)/$(@D); \ + DD=$(@D); \ + if [ ! -f $$SD/Makefile ]; then \ + SD=$(@D); \ + DD=$(notdir $(@D)); \ + fi; \ + if ([ ! -f $$DD/Makefile ] || \ + command test $$DD/Makefile -ot \ + $$SD/Makefile ); then \ + $(MKDIR) $$DD; \ + $(CP) $$SD/Makefile $$DD/Makefile; \ + fi; \ + $(MAKE) -C $$DD $(subst $(@D)/.make,,$@) +endif + +#--------------------------------------------------------- +# Handle the OPTIONAL_DIRS options for directores that may +# or may not exist. +#--------------------------------------------------------- +ifdef OPTIONAL_DIRS + +SubDirs += $(OPTIONAL_DIRS) + +ifneq ($(PROJ_SRC_ROOT),$(PROJ_OBJ_ROOT)) +$(RecursiveTargets):: + $(Verb) for dir in $(OPTIONAL_DIRS); do \ + if [ -d $(PROJ_SRC_DIR)/$$dir ]; then\ + if ([ ! -f $$dir/Makefile ] || \ + command test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ + $(MKDIR) $$dir; \ + $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ + fi; \ + ($(MAKE) -C$$dir $@ ) || exit 1; \ + fi \ + done +else +$(RecursiveTargets):: + $(Verb) for dir in $(OPTIONAL_DIRS); do \ + if [ -d $(PROJ_SRC_DIR)/$$dir ]; then\ + ($(MAKE) -C$$dir $@ ) || exit 1; \ + fi \ + done +endif +endif + +#--------------------------------------------------------- +# Handle the CONFIG_FILES options +#--------------------------------------------------------- +ifdef CONFIG_FILES + +ifdef NO_INSTALL +install-local:: + $(Echo) Install circumvented with NO_INSTALL +uninstall-local:: + $(Echo) UnInstall circumvented with NO_INSTALL +else +install-local:: $(DESTDIR)$(PROJ_etcdir) $(CONFIG_FILES) + $(Echo) Installing Configuration Files To $(DESTDIR)$(PROJ_etcdir) + $(Verb)for file in $(CONFIG_FILES); do \ + if test -f $(PROJ_OBJ_DIR)/$${file} ; then \ + $(DataInstall) $(PROJ_OBJ_DIR)/$${file} $(DESTDIR)$(PROJ_etcdir) ; \ + elif test -f $(PROJ_SRC_DIR)/$${file} ; then \ + $(DataInstall) $(PROJ_SRC_DIR)/$${file} $(DESTDIR)$(PROJ_etcdir) ; \ + else \ + $(ECHO) Error: cannot find config file $${file}. ; \ + fi \ + done + +uninstall-local:: + $(Echo) Uninstalling Configuration Files From $(DESTDIR)$(PROJ_etcdir) + $(Verb)for file in $(CONFIG_FILES); do \ + $(RM) -f $(DESTDIR)$(PROJ_etcdir)/$${file} ; \ + done +endif + +endif + +############################################################################### +# Set up variables for building libraries +############################################################################### + +#--------------------------------------------------------- +# Define various command line options pertaining to the +# libraries needed when linking. There are "Proj" libs +# (defined by the user's project) and "LLVM" libs (defined +# by the LLVM project). +#--------------------------------------------------------- + +ifdef USEDLIBS +ProjLibsOptions := $(patsubst %.a.o, -l%, $(addsuffix .o, $(USEDLIBS))) +ProjLibsOptions := $(patsubst %.o, $(LibDir)/%.o, $(ProjLibsOptions)) +ProjUsedLibs := $(patsubst %.a.o, lib%.a, $(addsuffix .o, $(USEDLIBS))) +ProjLibsPaths := $(addprefix $(LibDir)/,$(ProjUsedLibs)) +endif + +ifdef LLVMLIBS +LLVMLibsOptions := $(patsubst %.a.o, -l%, $(addsuffix .o, $(LLVMLIBS))) +LLVMLibsOptions := $(patsubst %.o, $(LLVMLibDir)/%.o, $(LLVMLibsOptions)) +LLVMUsedLibs := $(patsubst %.a.o, lib%.a, $(addsuffix .o, $(LLVMLIBS))) +LLVMLibsPaths := $(addprefix $(LLVMLibDir)/,$(LLVMUsedLibs)) +endif + +# Loadable module for Win32 requires all symbols resolved for linking. +# Then all symbols in LLVM.dll will be available. +ifeq ($(ENABLE_SHARED),1) + ifdef LOADABLE_MODULE + ifneq (,$(filter $(HOST_OS),Cygwin MingW)) + LINK_COMPONENTS += all + endif + endif +endif + +ifndef IS_CLEANING_TARGET +ifdef LINK_COMPONENTS + +# If LLVM_CONFIG doesn't exist, build it. This can happen if you do a make +# clean in tools, then do a make in tools (instead of at the top level). +$(LLVM_CONFIG): + @echo "*** llvm-config doesn't exist - rebuilding it." + @$(MAKE) -C $(PROJ_OBJ_ROOT)/tools/llvm-config + +$(ToolDir)/$(strip $(TOOLNAME))$(EXEEXT): $(LLVM_CONFIG) + +ifeq ($(ENABLE_SHARED), 1) +# We can take the "auto-import" feature to get rid of using dllimport. +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +LLVMLibsOptions += -Wl,--enable-auto-import,--enable-runtime-pseudo-reloc \ + -L $(SharedLibDir) +endif +LLVM_SO_NAME = LLVM-$(LLVM_VERSION_MAJOR).$(LLVM_VERSION_MINOR)$(LLVM_VERSION_SUFFIX) +LLVMLibsOptions += -l$(LLVM_SO_NAME) +LLVMLibsPaths += $(SharedLibDir)/$(SharedPrefix)$(LLVM_SO_NAME)$(SHLIBEXT) +else + +ifndef NO_LLVM_CONFIG +LLVMConfigLibs := $(shell $(LLVM_CONFIG) --libs $(LINK_COMPONENTS) || echo Error) +ifeq ($(LLVMConfigLibs),Error) +$(error llvm-config --libs failed) +endif +LLVMLibsOptions += $(LLVMConfigLibs) +LLVMConfigLibfiles := $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS) || echo Error) +ifeq ($(LLVMConfigLibfiles),Error) +$(error llvm-config --libfiles failed) +endif +LLVMLibsPaths += $(LLVM_CONFIG) $(LLVMConfigLibfiles) +endif + +endif +endif +endif + +# Set up the library exports file. +ifdef EXPORTED_SYMBOL_FILE + +# First, set up the native export file, which may differ from the source +# export file. + +ifeq ($(HOST_OS),Darwin) +# Darwin convention prefixes symbols with underscores. +NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE)).sed +$(NativeExportsFile): $(EXPORTED_SYMBOL_FILE) $(ObjDir)/.dir + $(Verb) sed -e 's/^/_/' < $< > $@ +clean-local:: + -$(Verb) $(RM) -f $(NativeExportsFile) +else +ifeq ($(HAVE_LINK_VERSION_SCRIPT),1) +# Gold and BFD ld require a version script rather than a plain list. +NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE)).map +$(NativeExportsFile): $(EXPORTED_SYMBOL_FILE) $(ObjDir)/.dir + $(Verb) echo "{" > $@ + $(Verb) grep -q '[[:alnum:]_]' $< && echo " global:" >> $@ || : + $(Verb) sed -e 's/$$/;/' -e 's/^/ /' < $< >> $@ +ifneq ($(HOST_OS),OpenBSD) + $(Verb) echo " local: *;" >> $@ +endif + $(Verb) echo "};" >> $@ +clean-local:: + -$(Verb) $(RM) -f $(NativeExportsFile) +else +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +# GNU ld Win32 accepts .DEF files that contain "DATA" entries. +NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE:.exports=.def)) +$(NativeExportsFile): $(EXPORTED_SYMBOL_FILE) $(ObjDir)/.dir + $(Echo) Generating $(notdir $@) + $(Verb) $(ECHO) "EXPORTS" > $@ + $(Verb) $(CAT) $< >> $@ +clean-local:: + -$(Verb) $(RM) -f $(NativeExportsFile) +else +# Default behavior: just use the exports file verbatim. +NativeExportsFile := $(EXPORTED_SYMBOL_FILE) +endif +endif +endif + +# Now add the linker command-line options to use the native export file. + +# Darwin +ifeq ($(HOST_OS),Darwin) +LLVMLibsOptions += -Wl,-exported_symbols_list,$(NativeExportsFile) +endif + +# gold, bfd ld, etc. +ifeq ($(HAVE_LINK_VERSION_SCRIPT),1) +LLVMLibsOptions += -Wl,--version-script,$(NativeExportsFile) +endif + +# Windows +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +# LLVMLibsOptions is invalidated at processing tools/llvm-shlib. +SharedLinkOptions += $(NativeExportsFile) +endif + +endif + +############################################################################### +# Library Build Rules: Four ways to build a library +############################################################################### + +# if we're building a library ... +ifdef LIBRARYNAME + +# Make sure there isn't any extraneous whitespace on the LIBRARYNAME option +LIBRARYNAME := $(strip $(LIBRARYNAME)) +LIBRARYALIASNAME := $(strip $(LIBRARYALIASNAME)) +ifdef LOADABLE_MODULE +BaseLibName.A := $(LIBRARYNAME).a +BaseLibName.SO := $(LIBRARYNAME)$(SHLIBEXT) +BaseAliasName.SO := $(LIBRARYALIASNAME)$(SHLIBEXT) +else +BaseLibName.A := lib$(LIBRARYNAME).a +BaseLibName.SO := $(SharedPrefix)$(LIBRARYNAME)$(SHLIBEXT) +BaseAliasName.SO := $(SharedPrefix)$(LIBRARYALIASNAME)$(SHLIBEXT) +endif +LibName.A := $(LibDir)/$(BaseLibName.A) +LibName.SO := $(SharedLibDir)/$(BaseLibName.SO) +AliasName.SO := $(SharedLibDir)/$(BaseAliasName.SO) +LibName.O := $(LibDir)/$(LIBRARYNAME).o + +#--------------------------------------------------------- +# Shared Library Targets: +# If the user asked for a shared library to be built +# with the SHARED_LIBRARY variable, then we provide +# targets for building them. +#--------------------------------------------------------- +ifdef SHARED_LIBRARY + +all-local:: $(AliasName.SO) + +$(AliasName.SO): $(LibName.SO) +ifdef SHARED_ALIAS + $(Verb) $(AliasTool) $(BaseLibName.SO) $(AliasName.SO) +endif + +ifdef EXPORTED_SYMBOL_FILE +$(LibName.SO): $(NativeExportsFile) +endif + +ifdef LINK_LIBS_IN_SHARED +ifdef LOADABLE_MODULE +SharedLibKindMessage := "Loadable Module" +SharedLinkOptions := $(LoadableModuleOptions) $(SharedLinkOptions) +else +SharedLibKindMessage := "Shared Library" +endif +$(LibName.SO): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) $(SharedLibDir)/.dir + $(Echo) Linking $(BuildMode) $(SharedLibKindMessage) \ + $(notdir $@) + $(Verb) $(Link) $(SharedLinkOptions) -o $@ $(ObjectsO) \ + $(ProjLibsOptions) $(LLVMLibsOptions) $(LIBS) +else +$(LibName.SO): $(ObjectsO) $(SharedLibDir)/.dir + $(Echo) Linking $(BuildMode) Shared Library $(notdir $@) + $(Verb) $(Link) $(SharedLinkOptions) -o $@ $(ObjectsO) +endif + +clean-local:: +ifneq ($(strip $(LibName.SO)),) + -$(Verb) $(RM) -f $(LibName.SO) +endif + +ifdef NO_INSTALL +install-local:: + $(Echo) Install circumvented with NO_INSTALL +uninstall-local:: + $(Echo) Uninstall circumvented with NO_INSTALL +else + +# Win32.DLL prefers to be located on the "PATH" of binaries. +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +DestSharedLibDir := $(DESTDIR)$(PROJ_bindir) +else +DestSharedLibDir := $(DESTDIR)$(PROJ_libdir) +endif +DestSharedLib := $(DestSharedLibDir)/$(BaseLibName.SO) +DestSharedAlias := $(DestSharedLibDir)/$(BaseAliasName.SO) + +install-local:: $(DestSharedLib) + +$(DestSharedLib): $(LibName.SO) $(DestSharedLibDir) + $(Echo) Installing $(BuildMode) Shared Library $(DestSharedLib) + $(Verb) $(INSTALL) $(LibName.SO) $(DestSharedLib) +ifdef SHARED_ALIAS + $(Echo) Creating alias from $(DestSharedLib) to $(DestSharedAlias) + $(Verb) $(AliasTool) $(BaseLibName.SO) $(DestSharedAlias) +endif + +uninstall-local:: + $(Echo) Uninstalling $(BuildMode) Shared Library $(DestSharedLib) + -$(Verb) $(RM) -f $(DestSharedLib) +ifdef SHARED_ALIAS + -$(Verb) $(RM) -f $(DestSharedAlias) +endif +endif +endif + +#--------------------------------------------------------- +# Library Targets: +# If neither BUILD_ARCHIVE or LOADABLE_MODULE are specified, default to +# building an archive. +#--------------------------------------------------------- +ifndef NO_BUILD_ARCHIVE +ifndef BUILD_ARCHIVE +ifndef LOADABLE_MODULE +BUILD_ARCHIVE = 1 +endif +endif +endif + +#--------------------------------------------------------- +# Archive Library Targets: +# If the user wanted a regular archive library built, +# then we provide targets for building them. +#--------------------------------------------------------- +ifdef BUILD_ARCHIVE + +all-local:: $(LibName.A) + +$(LibName.A): $(ObjectsO) $(LibDir)/.dir + $(Echo) Building $(BuildMode) Archive Library $(notdir $@) + -$(Verb) $(RM) -f $@ + $(Verb) $(Archive) $@ $(ObjectsO) + $(Verb) $(Ranlib) $@ + +clean-local:: +ifneq ($(strip $(LibName.A)),) + -$(Verb) $(RM) -f $(LibName.A) +endif + +ifdef NO_INSTALL +install-local:: + $(Echo) Install circumvented with NO_INSTALL +uninstall-local:: + $(Echo) Uninstall circumvented with NO_INSTALL +else +ifdef NO_INSTALL_ARCHIVES +install-local:: + $(Echo) Install circumvented with NO_INSTALL +uninstall-local:: + $(Echo) Uninstall circumvented with NO_INSTALL +else +DestArchiveLib := $(DESTDIR)$(PROJ_libdir)/lib$(LIBRARYNAME).a + +install-local:: $(DestArchiveLib) + +$(DestArchiveLib): $(LibName.A) $(DESTDIR)$(PROJ_libdir) + $(Echo) Installing $(BuildMode) Archive Library $(DestArchiveLib) + $(Verb) $(MKDIR) $(DESTDIR)$(PROJ_libdir) + $(Verb) $(INSTALL) $(LibName.A) $(DestArchiveLib) + +uninstall-local:: + $(Echo) Uninstalling $(BuildMode) Archive Library $(DestArchiveLib) + -$(Verb) $(RM) -f $(DestArchiveLib) +endif +endif +endif + +# endif LIBRARYNAME +endif + +############################################################################### +# Tool Build Rules: Build executable tool based on TOOLNAME option +############################################################################### + +ifdef TOOLNAME + +#--------------------------------------------------------- +# Set up variables for building a tool. +#--------------------------------------------------------- +TOOLEXENAME := $(strip $(TOOLNAME))$(EXEEXT) +ifdef EXAMPLE_TOOL +ToolBuildPath := $(ExmplDir)/$(TOOLEXENAME) +else +ToolBuildPath := $(ToolDir)/$(TOOLEXENAME) +endif + +# TOOLALIAS is a name to symlink (or copy) the tool to. +ifdef TOOLALIAS +ifdef EXAMPLE_TOOL +ToolAliasBuildPath := $(ExmplDir)/$(strip $(TOOLALIAS))$(EXEEXT) +else +ToolAliasBuildPath := $(ToolDir)/$(strip $(TOOLALIAS))$(EXEEXT) +endif +endif + +#--------------------------------------------------------- +# Prune Exports +#--------------------------------------------------------- + +# If the tool opts in with TOOL_NO_EXPORTS, optimize startup time of the app by +# not exporting all of the weak symbols from the binary. This reduces dyld +# startup time by 4x on darwin in some cases. +ifdef TOOL_NO_EXPORTS +ifeq ($(HOST_OS),Darwin) + +# Tiger tools don't support this. +ifneq ($(DARWIN_MAJVERS),4) +LD.Flags += -Wl,-exported_symbol,_main +endif +endif + +ifeq ($(HOST_OS), $(filter $(HOST_OS), DragonFly Linux NetBSD FreeBSD GNU/kFreeBSD GNU)) +ifneq ($(ARCH), Mips) + LD.Flags += -Wl,--version-script=$(LLVM_SRC_ROOT)/autoconf/ExportMap.map +endif +endif +endif + +#--------------------------------------------------------- +# Tool Order File Support +#--------------------------------------------------------- + +ifeq ($(HOST_OS),Darwin) +ifdef TOOL_ORDER_FILE + +LD.Flags += -Wl,-order_file,$(TOOL_ORDER_FILE) + +endif +endif + +#--------------------------------------------------------- +# Tool Version Info Support +#--------------------------------------------------------- + +ifeq ($(HOST_OS),Darwin) +ifdef TOOL_INFO_PLIST + +LD.Flags += -Wl,-sectcreate,__TEXT,__info_plist,$(ObjDir)/$(TOOL_INFO_PLIST) + +$(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST) + +$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in $(ObjDir)/.dir + $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..." + $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \ + -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \ + -e "s#@TOOL_INFO_VERSION@#$(TOOL_INFO_VERSION)#g" \ + -e "s#@TOOL_INFO_BUILD_VERSION@#$(TOOL_INFO_BUILD_VERSION)#g" \ + $< > $@ + +endif +endif + +#--------------------------------------------------------- +# Provide targets for building the tools +#--------------------------------------------------------- +all-local:: $(ToolBuildPath) $(ToolAliasBuildPath) + +clean-local:: +ifneq ($(strip $(ToolBuildPath)),) + -$(Verb) $(RM) -f $(ToolBuildPath) +endif +ifneq ($(strip $(ToolAliasBuildPath)),) + -$(Verb) $(RM) -f $(ToolAliasBuildPath) +endif + +ifdef EXAMPLE_TOOL +$(ToolBuildPath): $(ExmplDir)/.dir +else +$(ToolBuildPath): $(ToolDir)/.dir +endif + +ifdef CODESIGN_TOOLS +TOOL_CODESIGN_IDENTITY ?= - + +$(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) + $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) + $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) + $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ + $(StripWarnMsg) + $(Echo) ======= Code-Signing $(BuildMode) Executable $(TOOLNAME) + $(Verb) codesign -s $(TOOL_CODESIGN_IDENTITY) $@ +else +$(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) + $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) + $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) + $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ + $(StripWarnMsg) +endif + +ifneq ($(strip $(ToolAliasBuildPath)),) +$(ToolAliasBuildPath): $(ToolBuildPath) + $(Echo) Creating $(BuildMode) Alias $(TOOLALIAS) $(StripWarnMsg) + $(Verb) $(RM) -f $(ToolAliasBuildPath) + $(Verb) $(AliasTool) $(notdir $(ToolBuildPath)) $(ToolAliasBuildPath) + $(Echo) ======= Finished Creating $(BuildMode) Alias $(TOOLALIAS) \ + $(StripWarnMsg) +endif + +ifdef NO_INSTALL +install-local:: + $(Echo) Install circumvented with NO_INSTALL +uninstall-local:: + $(Echo) Uninstall circumvented with NO_INSTALL +else + +ifdef INTERNAL_TOOL +ToolBinDir = $(DESTDIR)$(PROJ_internal_prefix)/bin +else +ToolBinDir = $(DESTDIR)$(PROJ_bindir) +endif +DestTool = $(ToolBinDir)/$(program_prefix)$(TOOLEXENAME) + +install-local:: $(DestTool) + +$(DestTool): $(ToolBuildPath) + $(Echo) Installing $(BuildMode) $(DestTool) + $(Verb) $(MKDIR) $(ToolBinDir) + $(Verb) $(ProgInstall) $(ToolBuildPath) $(DestTool) + +uninstall-local:: + $(Echo) Uninstalling $(BuildMode) $(DestTool) + -$(Verb) $(RM) -f $(DestTool) + +# TOOLALIAS install. +ifdef TOOLALIAS +DestToolAlias = $(ToolBinDir)/$(program_prefix)$(TOOLALIAS)$(EXEEXT) + +install-local:: $(DestToolAlias) + +$(DestToolAlias): $(DestTool) + $(Echo) Installing $(BuildMode) $(DestToolAlias) + $(Verb) $(RM) -f $(DestToolAlias) + $(Verb) $(AliasTool) $(notdir $(DestTool)) $(DestToolAlias) + +uninstall-local:: + $(Echo) Uninstalling $(BuildMode) $(DestToolAlias) + -$(Verb) $(RM) -f $(DestToolAlias) +endif + +endif +endif + +############################################################################### +# Object Build Rules: Build object files based on sources +############################################################################### + +# FIXME: This should be checking for "if not GCC or ICC", not for "if HP-UX" +ifeq ($(HOST_OS),HP-UX) + DISABLE_AUTO_DEPENDENCIES=1 +endif + +COMPILE_DEPS = $(OBJECT_DIRS) $(BUILT_SOURCES) $(PROJ_MAKEFILE) + +# Provide rule sets for when dependency generation is enabled +ifndef DISABLE_AUTO_DEPENDENCIES + +#--------------------------------------------------------- +# Create .o files in the ObjDir directory from the .cpp and .c files... +#--------------------------------------------------------- + +DEPEND_OPTIONS = -MMD -MP -MF "$(ObjDir)/$*.d.tmp" \ + -MT "$(ObjDir)/$*.o" -MT "$(ObjDir)/$*.d" + +# If the build succeeded, move the dependency file over, otherwise +# remove it. +DEPEND_MOVEFILE = then $(MV) -f "$(ObjDir)/$*.d.tmp" "$(ObjDir)/$*.d"; \ + else $(RM) "$(ObjDir)/$*.d.tmp"; exit 1; fi + +$(ObjDir)/%.o: %.cpp $(COMPILE_DEPS) + $(Echo) "Compiling $*.cpp for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + +$(ObjDir)/%.o: %.mm $(COMPILE_DEPS) + $(Echo) "Compiling $*.mm for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + +$(ObjDir)/%.o: %.cc $(COMPILE_DEPS) + $(Echo) "Compiling $*.cc for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + +$(ObjDir)/%.o: %.c $(COMPILE_DEPS) + $(Echo) "Compiling $*.c for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + +$(ObjDir)/%.o: %.m $(COMPILE_DEPS) + $(Echo) "Compiling $*.m for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + +# Provide alternate rule sets if dependencies are disabled +else + +$(ObjDir)/%.o: %.cpp $(COMPILE_DEPS) + $(Echo) "Compiling $*.cpp for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ + +$(ObjDir)/%.o: %.mm $(COMPILE_DEPS) + $(Echo) "Compiling $*.mm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ + +$(ObjDir)/%.o: %.cc $(COMPILE_DEPS) + $(Echo) "Compiling $*.cc for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ + +$(ObjDir)/%.o: %.c $(COMPILE_DEPS) + $(Echo) "Compiling $*.c for $(BuildMode) build" $(PIC_FLAG) + $(Compile.C) $< -o $@ + +$(ObjDir)/%.o: %.m $(COMPILE_DEPS) + $(Echo) "Compiling $*.m for $(BuildMode) build" $(PIC_FLAG) + $(Compile.C) $< -o $@ +endif + + +## Rules for building preprocessed (.i/.ii) outputs. +$(BuildMode)/%.ii: %.cpp $(COMPILE_DEPS) + $(Echo) "Compiling $*.cpp for $(BuildMode) build to .ii file" + $(Verb) $(Preprocess.CXX) $< -o $@ + +$(BuildMode)/%.ii: %.mm $(COMPILE_DEPS) + $(Echo) "Compiling $*.mm for $(BuildMode) build to .ii file" + $(Verb) $(Preprocess.CXX) $< -o $@ + +$(BuildMode)/%.ii: %.cc $(COMPILE_DEPS) + $(Echo) "Compiling $*.cc for $(BuildMode) build to .ii file" + $(Verb) $(Preprocess.CXX) $< -o $@ + +$(BuildMode)/%.i: %.c $(COMPILE_DEPS) + $(Echo) "Compiling $*.c for $(BuildMode) build to .i file" + $(Verb) $(Preprocess.C) $< -o $@ + +$(BuildMode)/%.i: %.m $(COMPILE_DEPS) + $(Echo) "Compiling $*.m for $(BuildMode) build to .i file" + $(Verb) $(Preprocess.C) $< -o $@ + + +$(ObjDir)/%.s: %.cpp $(COMPILE_DEPS) + $(Echo) "Compiling $*.cpp to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ -S + +$(ObjDir)/%.s: %.mm $(COMPILE_DEPS) + $(Echo) "Compiling $*.mm to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ -S + +$(ObjDir)/%.s: %.cc $(COMPILE_DEPS) + $(Echo) "Compiling $*.cc to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ -S + +$(ObjDir)/%.s: %.c $(COMPILE_DEPS) + $(Echo) "Compiling $*.c to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.C) $< -o $@ -S + +$(ObjDir)/%.s: %.m $(COMPILE_DEPS) + $(Echo) "Compiling $*.m to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.C) $< -o $@ -S + +############################################################################### +# TABLEGEN: Provide rules for running tblgen to produce *.inc files +############################################################################### + +ifdef TARGET +TABLEGEN_INC_FILES_COMMON = 1 +endif + +ifdef TABLEGEN_INC_FILES_COMMON + +INCFiles := $(filter %.inc,$(BUILT_SOURCES)) +INCTMPFiles := $(INCFiles:%=$(ObjDir)/%.tmp) +.PRECIOUS: $(INCTMPFiles) $(INCFiles) + +# INCFiles rule: All of the tblgen generated files are emitted to +# $(ObjDir)/%.inc.tmp, instead of emitting them directly to %.inc. This allows +# us to only "touch" the real file if the contents of it change. IOW, if +# tblgen is modified, all of the .inc.tmp files are regenerated, but no +# dependencies of the .inc files are, unless the contents of the .inc file +# changes. +$(INCFiles) : %.inc : $(ObjDir)/%.inc.tmp + $(Verb) $(CMP) -s $@ $< || $(CP) $< $@ + +endif # TABLEGEN_INC_FILES_COMMON + +ifdef TARGET + +TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \ + $(LLVM_SRC_ROOT)/include/llvm/Target/Target.td \ + $(LLVM_SRC_ROOT)/include/llvm/Target/TargetCallingConv.td \ + $(LLVM_SRC_ROOT)/include/llvm/Target/TargetSchedule.td \ + $(LLVM_SRC_ROOT)/include/llvm/Target/TargetSelectionDAG.td \ + $(LLVM_SRC_ROOT)/include/llvm/CodeGen/ValueTypes.td) \ + $(wildcard $(LLVM_SRC_ROOT)/include/llvm/IR/Intrinsics*.td) + +# All .inc.tmp files depend on the .td files. +$(INCTMPFiles) : $(TDFiles) + +$(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \ +$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN) + $(Echo) "Building $(.td.expanded. This is useful for debugging. +$(TARGET:%=%.td.expanded): \ +%.td.expanded : %.td $(LLVM_TBLGEN) $(TDFiles) + $(Echo) "Building a fully expanded version of $( $@ +else +%.ps: %.dot + $(Echo) "Cannot build $@: The program dot is not installed" +endif + +# This rules ensures that header files that are removed still have a rule for +# which they can be "generated." This allows make to ignore them and +# reproduce the dependency lists. +%.h:: ; +%.hpp:: ; + +# Define clean-local to clean the current directory. Note that this uses a +# very conservative approach ensuring that empty variables do not cause +# errors or disastrous removal. +clean-local:: +ifneq ($(strip $(ObjRootDir)),) + -$(Verb) $(RM) -rf $(ObjRootDir) +endif +ifneq ($(strip $(SHLIBEXT)),) # Extra paranoia - make real sure SHLIBEXT is set + -$(Verb) $(RM) -f *$(SHLIBEXT) +endif + +clean-all-local:: + -$(Verb) $(RM) -rf Debug Release Profile + + +############################################################################### +# DEPENDENCIES: Include the dependency files if we should +############################################################################### +ifndef DISABLE_AUTO_DEPENDENCIES + +# If its not one of the cleaning targets +ifndef IS_CLEANING_TARGET + +# Get the list of dependency files +DependSourceFiles := $(basename $(filter %.cpp %.c %.cc %.m %.mm, $(Sources))) +DependFiles := $(DependSourceFiles:%=$(PROJ_OBJ_DIR)/$(BuildMode)/%.d) + +-include $(DependFiles) "" + +endif + +endif + +############################################################################### +# CHECK: Running the test suite +############################################################################### + +check:: + $(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \ + if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \ + $(EchoCmd) Running test suite ; \ + $(MAKE) -C $(PROJ_OBJ_ROOT)/test check-local \ + TESTSUITE=$(TESTSUITE) ; \ + else \ + $(EchoCmd) No Makefile in test directory ; \ + fi ; \ + else \ + $(EchoCmd) No test directory ; \ + fi + +# An alias dating from when both lit and DejaGNU test runners were used. +check-lit:: check + +check-all:: + $(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \ + if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \ + $(EchoCmd) Running test suite ; \ + $(MAKE) -C $(PROJ_OBJ_ROOT)/test check-local-all ; \ + else \ + $(EchoCmd) No Makefile in test directory ; \ + fi ; \ + else \ + $(EchoCmd) No test directory ; \ + fi + +############################################################################### +# UNITTESTS: Running the unittests test suite +############################################################################### + +unittests:: + $(Verb) if test -d "$(PROJ_OBJ_ROOT)/unittests" ; then \ + if test -f "$(PROJ_OBJ_ROOT)/unittests/Makefile" ; then \ + $(EchoCmd) Running unittests test suite ; \ + $(MAKE) -C $(PROJ_OBJ_ROOT)/unittests unitcheck; \ + else \ + $(EchoCmd) No Makefile in unittests directory ; \ + fi ; \ + else \ + $(EchoCmd) No unittests directory ; \ + fi + +############################################################################### +# DISTRIBUTION: Handle construction of a distribution tarball +############################################################################### + +#------------------------------------------------------------------------ +# Define distribution related variables +#------------------------------------------------------------------------ +DistName := $(PROJECT_NAME)-$(PROJ_VERSION) +DistDir := $(PROJ_OBJ_ROOT)/$(DistName) +TopDistDir := $(PROJ_OBJ_ROOT)/$(DistName) +DistTarGZip := $(PROJ_OBJ_ROOT)/$(DistName).tar.gz +DistZip := $(PROJ_OBJ_ROOT)/$(DistName).zip +DistTarBZ2 := $(PROJ_OBJ_ROOT)/$(DistName).tar.bz2 +DistAlways := CREDITS.TXT LICENSE.TXT README.txt README AUTHORS COPYING \ + ChangeLog INSTALL NEWS Makefile Makefile.common Makefile.rules \ + Makefile.config.in configure autoconf +DistOther := $(notdir $(wildcard \ + $(PROJ_SRC_DIR)/*.h \ + $(PROJ_SRC_DIR)/*.td \ + $(PROJ_SRC_DIR)/*.def \ + $(PROJ_SRC_DIR)/*.ll \ + $(PROJ_SRC_DIR)/*.in)) +DistSubDirs := $(SubDirs) +DistSources = $(Sources) $(EXTRA_DIST) +DistFiles = $(DistAlways) $(DistSources) $(DistOther) + +#------------------------------------------------------------------------ +# We MUST build distribution with OBJ_DIR != SRC_DIR +#------------------------------------------------------------------------ +ifeq ($(PROJ_SRC_DIR),$(PROJ_OBJ_DIR)) +dist dist-check dist-clean dist-gzip dist-bzip2 dist-zip :: + $(Echo) ERROR: Target $@ only available with OBJ_DIR != SRC_DIR + +else + +#------------------------------------------------------------------------ +# Prevent attempt to run dist targets from anywhere but the top level +#------------------------------------------------------------------------ +ifneq ($(LEVEL),.) +dist dist-check dist-clean dist-gzip dist-bzip2 dist-zip :: + $(Echo) ERROR: You must run $@ from $(PROJ_OBJ_ROOT) +else + +#------------------------------------------------------------------------ +# Provide the top level targets +#------------------------------------------------------------------------ + +dist-gzip:: $(DistTarGZip) + +$(DistTarGZip) : $(TopDistDir)/.makedistdir + $(Echo) Packing gzipped distribution tar file. + $(Verb) cd $(PROJ_OBJ_ROOT) ; $(TAR) chf - "$(DistName)" | \ + $(GZIP) -c > "$(DistTarGZip)" + +dist-bzip2:: $(DistTarBZ2) + +$(DistTarBZ2) : $(TopDistDir)/.makedistdir + $(Echo) Packing bzipped distribution tar file. + $(Verb) cd $(PROJ_OBJ_ROOT) ; $(TAR) chf - $(DistName) | \ + $(BZIP2) -c >$(DistTarBZ2) + +dist-zip:: $(DistZip) + +$(DistZip) : $(TopDistDir)/.makedistdir + $(Echo) Packing zipped distribution file. + $(Verb) rm -f $(DistZip) + $(Verb) cd $(PROJ_OBJ_ROOT) ; $(ZIP) -rq $(DistZip) $(DistName) + +dist :: $(DistTarGZip) $(DistTarBZ2) $(DistZip) + $(Echo) ===== DISTRIBUTION PACKAGING SUCCESSFUL ===== + +DistCheckDir := $(PROJ_OBJ_ROOT)/_distcheckdir + +dist-check:: $(DistTarGZip) + $(Echo) Checking distribution tar file. + $(Verb) if test -d $(DistCheckDir) ; then \ + $(RM) -rf $(DistCheckDir) ; \ + fi + $(Verb) $(MKDIR) $(DistCheckDir) + $(Verb) cd $(DistCheckDir) && \ + $(MKDIR) $(DistCheckDir)/build && \ + $(MKDIR) $(DistCheckDir)/install && \ + gunzip -c $(DistTarGZip) | $(TAR) xf - && \ + cd build && \ + ../$(DistName)/configure --prefix="$(DistCheckDir)/install" \ + --srcdir=../$(DistName) $(DIST_CHECK_CONFIG_OPTIONS) && \ + $(MAKE) all && \ + $(MAKE) check && \ + $(MAKE) unittests && \ + $(MAKE) install && \ + $(MAKE) uninstall && \ + $(MAKE) dist-clean && \ + $(EchoCmd) ===== $(DistTarGZip) Ready For Distribution ===== + +dist-clean:: + $(Echo) Cleaning distribution files + -$(Verb) $(RM) -rf $(DistTarGZip) $(DistTarBZ2) $(DistZip) $(DistName) \ + $(DistCheckDir) + +endif + +#------------------------------------------------------------------------ +# Provide the recursive distdir target for building the distribution directory +#------------------------------------------------------------------------ +distdir: $(DistDir)/.makedistdir +$(DistDir)/.makedistdir: $(DistSources) + $(Verb) if test "$(DistDir)" = "$(TopDistDir)" ; then \ + if test -d "$(DistDir)" ; then \ + find $(DistDir) -type d ! -perm -200 -exec chmod u+w {} ';' || \ + exit 1 ; \ + fi ; \ + $(EchoCmd) Removing old $(DistDir) ; \ + $(RM) -rf $(DistDir); \ + $(EchoCmd) Making 'all' to verify build ; \ + $(MAKE) ENABLE_OPTIMIZED=1 all ; \ + fi + $(Echo) Building Distribution Directory $(DistDir) + $(Verb) $(MKDIR) $(DistDir) + $(Verb) srcdirstrip=`echo "$(PROJ_SRC_DIR)" | sed 's|.|.|g'`; \ + srcrootstrip=`echo "$(PROJ_SRC_ROOT)" | sed 's|.|.|g'`; \ + for file in $(DistFiles) ; do \ + case "$$file" in \ + $(PROJ_SRC_DIR)/*) \ + file=`echo "$$file" | sed "s#^$$srcdirstrip/##"` \ + ;; \ + $(PROJ_SRC_ROOT)/*) \ + file=`echo "$$file" | \ + sed "s#^$$srcrootstrip/##"` \ + ;; \ + esac; \ + if test -f "$(PROJ_SRC_DIR)/$$file" || \ + test -d "$(PROJ_SRC_DIR)/$$file" ; then \ + from_dir="$(PROJ_SRC_DIR)" ; \ + elif test -f "$$file" || test -d "$$file" ; then \ + from_dir=. ; \ + fi ; \ + to_dir=`echo "$$file" | sed -e 's#/[^/]*$$##'` ; \ + if test "$$to_dir" != "$$file" && test "$$to_dir" != "."; then \ + to_dir="$(DistDir)/$$dir"; \ + $(MKDIR) "$$to_dir" ; \ + else \ + to_dir="$(DistDir)"; \ + fi; \ + mid_dir=`echo "$$file" | sed -n -e 's#^\(.*\)/[^/]*$$#\1#p'`; \ + if test -n "$$mid_dir" ; then \ + $(MKDIR) "$$to_dir/$$mid_dir" || exit 1; \ + fi ; \ + if test -d "$$from_dir/$$file"; then \ + if test -d "$(PROJ_SRC_DIR)/$$file" && \ + test "$$from_dir" != "$(PROJ_SRC_DIR)" ; then \ + cd $(PROJ_SRC_DIR) ; \ + $(TAR) cf - $$file --exclude .svn --exclude CVS | \ + ( cd $$to_dir ; $(TAR) xf - ) ; \ + cd $(PROJ_OBJ_DIR) ; \ + else \ + cd $$from_dir ; \ + $(TAR) cf - $$file --exclude .svn --exclude CVS | \ + ( cd $$to_dir ; $(TAR) xf - ) ; \ + cd $(PROJ_OBJ_DIR) ; \ + fi; \ + elif test -f "$$from_dir/$$file" ; then \ + $(CP) -p "$$from_dir/$$file" "$(DistDir)/$$file" || exit 1; \ + elif test -L "$$from_dir/$$file" ; then \ + $(CP) -pd "$$from_dir/$$file" $(DistDir)/$$file || exit 1; \ + elif echo "$(DistAlways)" | grep -v "$$file" >/dev/null ; then \ + $(EchoCmd) "===== WARNING: Distribution Source " \ + "$$from_dir/$$file Not Found!" ; \ + elif test "$(Verb)" != '@' ; then \ + $(EchoCmd) "Skipping non-existent $$from_dir/$$file" ; \ + fi; \ + done + $(Verb) for subdir in $(DistSubDirs) ; do \ + if test "$$subdir" \!= "." ; then \ + new_distdir="$(DistDir)/$$subdir" ; \ + test -d "$$new_distdir" || $(MKDIR) "$$new_distdir" || exit 1; \ + ( cd $$subdir && $(MAKE) ENABLE_OPTIMIZED=1 \ + DistDir="$$new_distdir" distdir ) || exit 1; \ + fi; \ + done + $(Verb) if test "$(DistDir)" = "$(TopDistDir)" ; then \ + $(EchoCmd) Eliminating CVS/.svn directories from distribution ; \ + $(RM) -rf `find $(TopDistDir) -type d \( -name CVS -o \ + -name .svn \) -print` ;\ + $(MAKE) dist-hook ; \ + $(FIND) $(TopDistDir) -type d ! -perm -777 -exec chmod a+rwx {} \; \ + -o ! -type d ! -perm -444 -links 1 -exec chmod a+r {} \; \ + -o ! -type d ! -perm -400 -exec chmod a+r {} \; \ + -o ! -type d ! -perm -444 -exec \ + $(SHELL) $(INSTALL_SH) -c -m a+r {} {} \; \ + || chmod -R a+r $(DistDir) ; \ + fi + +# This is invoked by distdir target, define it as a no-op to avoid errors if not +# defined by user. +dist-hook:: + +endif + +############################################################################### +# TOP LEVEL - targets only to apply at the top level directory +############################################################################### + +ifeq ($(LEVEL),.) + +#------------------------------------------------------------------------ +# Install support for the project's include files: +#------------------------------------------------------------------------ +ifdef NO_INSTALL +install-local:: + $(Echo) Install circumvented with NO_INSTALL +uninstall-local:: + $(Echo) Uninstall circumvented with NO_INSTALL +else +install-local:: + $(Echo) Installing include files + $(Verb) $(MKDIR) $(DESTDIR)$(PROJ_includedir) + $(Verb) if test -d "$(PROJ_SRC_ROOT)/include" ; then \ + cd $(PROJ_SRC_ROOT)/include && \ + for hdr in `find . -type f \ + '(' -name LICENSE.TXT \ + -o -name '*.def' \ + -o -name '*.h' \ + -o -name '*.inc' \ + -o -name '*.td' \ + ')' -print | grep -v CVS | \ + grep -v .svn` ; do \ + instdir=`dirname "$(DESTDIR)$(PROJ_includedir)/$$hdr"` ; \ + if test \! -d "$$instdir" ; then \ + $(EchoCmd) Making install directory $$instdir ; \ + $(MKDIR) $$instdir ;\ + fi ; \ + $(DataInstall) $$hdr $(DESTDIR)$(PROJ_includedir)/$$hdr ; \ + done ; \ + fi +ifneq ($(PROJ_SRC_ROOT),$(PROJ_OBJ_ROOT)) + $(Verb) if test -d "$(PROJ_OBJ_ROOT)/include" ; then \ + cd $(PROJ_OBJ_ROOT)/include && \ + for hdr in `find . -type f \ + '(' -name LICENSE.TXT \ + -o -name '*.def' \ + -o -name '*.h' \ + -o -name '*.inc' \ + -o -name '*.td' \ + ')' -print | grep -v CVS | \ + grep -v .svn` ; do \ + instdir=`dirname "$(DESTDIR)$(PROJ_includedir)/$$hdr"` ; \ + if test \! -d "$$instdir" ; then \ + $(EchoCmd) Making install directory $$instdir ; \ + $(MKDIR) $$instdir ;\ + fi ; \ + $(DataInstall) $$hdr $(DESTDIR)$(PROJ_includedir)/$$hdr ; \ + done ; \ + fi +endif + +uninstall-local:: + $(Echo) Uninstalling include files + $(Verb) if [ -d "$(PROJ_SRC_ROOT)/include" ] ; then \ + cd $(PROJ_SRC_ROOT)/include && \ + $(RM) -f `find . -path '*/Internal' -prune -o '(' -type f \ + '!' '(' -name '*~' -o -name '.#*' \ + -o -name '*.in' ')' -print ')' | \ + grep -v CVS | sed 's#^#$(DESTDIR)$(PROJ_includedir)/#'` ; \ + cd $(PROJ_SRC_ROOT)/include && \ + $(RM) -f `find . -path '*/Internal' -prune -o '(' -type f -name '*.in' \ + -print ')' | sed 's#\.in$$##;s#^#$(DESTDIR)$(PROJ_includedir)/#'` ; \ + fi +endif +endif + +check-line-length: + @echo searching for overlength lines in files: $(Sources) + @echo + @echo + egrep -n '.{81}' $(Sources) /dev/null + +check-for-tabs: + @echo searching for tabs in files: $(Sources) + @echo + @echo + egrep -n ' ' $(Sources) /dev/null + +check-footprint: + @ls -l $(LibDir) | awk '\ + BEGIN { sum = 0; } \ + { sum += $$5; } \ + END { printf("Libraries: %6.3f MBytes\n", sum/(1024.0*1024.0)); }' + @ls -l $(ToolDir) | awk '\ + BEGIN { sum = 0; } \ + { sum += $$5; } \ + END { printf("Programs: %6.3f MBytes\n", sum/(1024.0*1024.0)); }' +#------------------------------------------------------------------------ +# Print out the directories used for building +#------------------------------------------------------------------------ +printvars:: + $(Echo) "BuildMode : " '$(BuildMode)' + $(Echo) "PROJ_SRC_ROOT: " '$(PROJ_SRC_ROOT)' + $(Echo) "PROJ_SRC_DIR : " '$(PROJ_SRC_DIR)' + $(Echo) "PROJ_OBJ_ROOT: " '$(PROJ_OBJ_ROOT)' + $(Echo) "PROJ_OBJ_DIR : " '$(PROJ_OBJ_DIR)' + $(Echo) "LLVM_SRC_ROOT: " '$(LLVM_SRC_ROOT)' + $(Echo) "LLVM_OBJ_ROOT: " '$(LLVM_OBJ_ROOT)' + $(Echo) "PROJ_prefix : " '$(PROJ_prefix)' + $(Echo) "PROJ_internal_prefix : " '$(PROJ_internal_prefix)' + $(Echo) "PROJ_bindir : " '$(PROJ_bindir)' + $(Echo) "PROJ_libdir : " '$(PROJ_libdir)' + $(Echo) "PROJ_etcdir : " '$(PROJ_etcdir)' + $(Echo) "PROJ_includedir : " '$(PROJ_includedir)' + $(Echo) "UserTargets : " '$(UserTargets)' + $(Echo) "ObjMakefiles : " '$(ObjMakefiles)' + $(Echo) "SrcMakefiles : " '$(SrcMakefiles)' + $(Echo) "ObjDir : " '$(ObjDir)' + $(Echo) "LibDir : " '$(LibDir)' + $(Echo) "ToolDir : " '$(ToolDir)' + $(Echo) "ExmplDir : " '$(ExmplDir)' + $(Echo) "Sources : " '$(Sources)' + $(Echo) "TDFiles : " '$(TDFiles)' + $(Echo) "INCFiles : " '$(INCFiles)' + $(Echo) "INCTMPFiles : " '$(INCTMPFiles)' + $(Echo) "PreConditions: " '$(PreConditions)' + $(Echo) "Compile.CXX : " '$(Compile.CXX)' + $(Echo) "Compile.C : " '$(Compile.C)' + $(Echo) "Archive : " '$(Archive)' + $(Echo) "YaccFiles : " '$(YaccFiles)' + $(Echo) "LexFiles : " '$(LexFiles)' + $(Echo) "Module : " '$(Module)' + $(Echo) "FilesToConfig: " '$(FilesToConfigPATH)' + $(Echo) "SubDirs : " '$(SubDirs)' + $(Echo) "ProjLibsPaths: " '$(ProjLibsPaths)' + $(Echo) "ProjLibsOptions: " '$(ProjLibsOptions)' + +### +# Debugging + +# General debugging rule, use 'make dbg-print-XXX' to print the +# definition, value and origin of XXX. +make-print-%: + $(error PRINT: $(value $*) = "$($*)" (from $(origin $*))) diff -pruN 1:3.6.2-3/.pc/rL235088.diff/lib/Target/AArch64/AArch64InstrInfo.cpp 1:3.6.2-4/.pc/rL235088.diff/lib/Target/AArch64/AArch64InstrInfo.cpp --- 1:3.6.2-3/.pc/rL235088.diff/lib/Target/AArch64/AArch64InstrInfo.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 1:3.6.2-4/.pc/rL235088.diff/lib/Target/AArch64/AArch64InstrInfo.cpp 2015-01-14 11:23:27.000000000 +0000 @@ -0,0 +1,2960 @@ +//===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the AArch64 implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#include "AArch64InstrInfo.h" +#include "AArch64MachineCombinerPattern.h" +#include "AArch64Subtarget.h" +#include "MCTargetDesc/AArch64AddressingModes.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define GET_INSTRINFO_CTOR_DTOR +#include "AArch64GenInstrInfo.inc" + +AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) + : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), + RI(this, &STI), Subtarget(STI) {} + +/// GetInstSize - Return the number of bytes of code the specified +/// instruction may be. This returns the maximum number of bytes. +unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { + const MachineBasicBlock &MBB = *MI->getParent(); + const MachineFunction *MF = MBB.getParent(); + const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); + + if (MI->getOpcode() == AArch64::INLINEASM) + return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); + + const MCInstrDesc &Desc = MI->getDesc(); + switch (Desc.getOpcode()) { + default: + // Anything not explicitly designated otherwise is a nomal 4-byte insn. + return 4; + case TargetOpcode::DBG_VALUE: + case TargetOpcode::EH_LABEL: + case TargetOpcode::IMPLICIT_DEF: + case TargetOpcode::KILL: + return 0; + } + + llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size"); +} + +static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, + SmallVectorImpl &Cond) { + // Block ends with fall-through condbranch. + switch (LastInst->getOpcode()) { + default: + llvm_unreachable("Unknown branch instruction?"); + case AArch64::Bcc: + Target = LastInst->getOperand(1).getMBB(); + Cond.push_back(LastInst->getOperand(0)); + break; + case AArch64::CBZW: + case AArch64::CBZX: + case AArch64::CBNZW: + case AArch64::CBNZX: + Target = LastInst->getOperand(1).getMBB(); + Cond.push_back(MachineOperand::CreateImm(-1)); + Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); + Cond.push_back(LastInst->getOperand(0)); + break; + case AArch64::TBZW: + case AArch64::TBZX: + case AArch64::TBNZW: + case AArch64::TBNZX: + Target = LastInst->getOperand(2).getMBB(); + Cond.push_back(MachineOperand::CreateImm(-1)); + Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); + Cond.push_back(LastInst->getOperand(0)); + Cond.push_back(LastInst->getOperand(1)); + } +} + +// Branch analysis. +bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { + // If the block has no terminators, it just falls into the block after it. + MachineBasicBlock::iterator I = MBB.end(); + if (I == MBB.begin()) + return false; + --I; + while (I->isDebugValue()) { + if (I == MBB.begin()) + return false; + --I; + } + if (!isUnpredicatedTerminator(I)) + return false; + + // Get the last instruction in the block. + MachineInstr *LastInst = I; + + // If there is only one terminator instruction, process it. + unsigned LastOpc = LastInst->getOpcode(); + if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { + if (isUncondBranchOpcode(LastOpc)) { + TBB = LastInst->getOperand(0).getMBB(); + return false; + } + if (isCondBranchOpcode(LastOpc)) { + // Block ends with fall-through condbranch. + parseCondBranch(LastInst, TBB, Cond); + return false; + } + return true; // Can't handle indirect branch. + } + + // Get the instruction before it if it is a terminator. + MachineInstr *SecondLastInst = I; + unsigned SecondLastOpc = SecondLastInst->getOpcode(); + + // If AllowModify is true and the block ends with two or more unconditional + // branches, delete all but the first unconditional branch. + if (AllowModify && isUncondBranchOpcode(LastOpc)) { + while (isUncondBranchOpcode(SecondLastOpc)) { + LastInst->eraseFromParent(); + LastInst = SecondLastInst; + LastOpc = LastInst->getOpcode(); + if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { + // Return now the only terminator is an unconditional branch. + TBB = LastInst->getOperand(0).getMBB(); + return false; + } else { + SecondLastInst = I; + SecondLastOpc = SecondLastInst->getOpcode(); + } + } + } + + // If there are three terminators, we don't know what sort of block this is. + if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) + return true; + + // If the block ends with a B and a Bcc, handle it. + if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { + parseCondBranch(SecondLastInst, TBB, Cond); + FBB = LastInst->getOperand(0).getMBB(); + return false; + } + + // If the block ends with two unconditional branches, handle it. The second + // one is not executed, so remove it. + if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { + TBB = SecondLastInst->getOperand(0).getMBB(); + I = LastInst; + if (AllowModify) + I->eraseFromParent(); + return false; + } + + // ...likewise if it ends with an indirect branch followed by an unconditional + // branch. + if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { + I = LastInst; + if (AllowModify) + I->eraseFromParent(); + return true; + } + + // Otherwise, can't handle this. + return true; +} + +bool AArch64InstrInfo::ReverseBranchCondition( + SmallVectorImpl &Cond) const { + if (Cond[0].getImm() != -1) { + // Regular Bcc + AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); + Cond[0].setImm(AArch64CC::getInvertedCondCode(CC)); + } else { + // Folded compare-and-branch + switch (Cond[1].getImm()) { + default: + llvm_unreachable("Unknown conditional branch!"); + case AArch64::CBZW: + Cond[1].setImm(AArch64::CBNZW); + break; + case AArch64::CBNZW: + Cond[1].setImm(AArch64::CBZW); + break; + case AArch64::CBZX: + Cond[1].setImm(AArch64::CBNZX); + break; + case AArch64::CBNZX: + Cond[1].setImm(AArch64::CBZX); + break; + case AArch64::TBZW: + Cond[1].setImm(AArch64::TBNZW); + break; + case AArch64::TBNZW: + Cond[1].setImm(AArch64::TBZW); + break; + case AArch64::TBZX: + Cond[1].setImm(AArch64::TBNZX); + break; + case AArch64::TBNZX: + Cond[1].setImm(AArch64::TBZX); + break; + } + } + + return false; +} + +unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator I = MBB.end(); + if (I == MBB.begin()) + return 0; + --I; + while (I->isDebugValue()) { + if (I == MBB.begin()) + return 0; + --I; + } + if (!isUncondBranchOpcode(I->getOpcode()) && + !isCondBranchOpcode(I->getOpcode())) + return 0; + + // Remove the branch. + I->eraseFromParent(); + + I = MBB.end(); + + if (I == MBB.begin()) + return 1; + --I; + if (!isCondBranchOpcode(I->getOpcode())) + return 1; + + // Remove the branch. + I->eraseFromParent(); + return 2; +} + +void AArch64InstrInfo::instantiateCondBranch( + MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB, + const SmallVectorImpl &Cond) const { + if (Cond[0].getImm() != -1) { + // Regular Bcc + BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB); + } else { + // Folded compare-and-branch + // Note that we use addOperand instead of addReg to keep the flags. + const MachineInstrBuilder MIB = + BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]); + if (Cond.size() > 3) + MIB.addImm(Cond[3].getImm()); + MIB.addMBB(TBB); + } +} + +unsigned AArch64InstrInfo::InsertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + const SmallVectorImpl &Cond, DebugLoc DL) const { + // Shouldn't be a fall through. + assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + + if (!FBB) { + if (Cond.empty()) // Unconditional branch? + BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB); + else + instantiateCondBranch(MBB, DL, TBB, Cond); + return 1; + } + + // Two-way conditional branch. + instantiateCondBranch(MBB, DL, TBB, Cond); + BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB); + return 2; +} + +// Find the original register that VReg is copied from. +static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { + while (TargetRegisterInfo::isVirtualRegister(VReg)) { + const MachineInstr *DefMI = MRI.getVRegDef(VReg); + if (!DefMI->isFullCopy()) + return VReg; + VReg = DefMI->getOperand(1).getReg(); + } + return VReg; +} + +// Determine if VReg is defined by an instruction that can be folded into a +// csel instruction. If so, return the folded opcode, and the replacement +// register. +static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, + unsigned *NewVReg = nullptr) { + VReg = removeCopies(MRI, VReg); + if (!TargetRegisterInfo::isVirtualRegister(VReg)) + return 0; + + bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); + const MachineInstr *DefMI = MRI.getVRegDef(VReg); + unsigned Opc = 0; + unsigned SrcOpNum = 0; + switch (DefMI->getOpcode()) { + case AArch64::ADDSXri: + case AArch64::ADDSWri: + // if NZCV is used, do not fold. + if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) + return 0; + // fall-through to ADDXri and ADDWri. + case AArch64::ADDXri: + case AArch64::ADDWri: + // add x, 1 -> csinc. + if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 || + DefMI->getOperand(3).getImm() != 0) + return 0; + SrcOpNum = 1; + Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; + break; + + case AArch64::ORNXrr: + case AArch64::ORNWrr: { + // not x -> csinv, represented as orn dst, xzr, src. + unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); + if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) + return 0; + SrcOpNum = 2; + Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; + break; + } + + case AArch64::SUBSXrr: + case AArch64::SUBSWrr: + // if NZCV is used, do not fold. + if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) + return 0; + // fall-through to SUBXrr and SUBWrr. + case AArch64::SUBXrr: + case AArch64::SUBWrr: { + // neg x -> csneg, represented as sub dst, xzr, src. + unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); + if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) + return 0; + SrcOpNum = 2; + Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; + break; + } + default: + return 0; + } + assert(Opc && SrcOpNum && "Missing parameters"); + + if (NewVReg) + *NewVReg = DefMI->getOperand(SrcOpNum).getReg(); + return Opc; +} + +bool AArch64InstrInfo::canInsertSelect( + const MachineBasicBlock &MBB, const SmallVectorImpl &Cond, + unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, + int &FalseCycles) const { + // Check register classes. + const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + const TargetRegisterClass *RC = + RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); + if (!RC) + return false; + + // Expanding cbz/tbz requires an extra cycle of latency on the condition. + unsigned ExtraCondLat = Cond.size() != 1; + + // GPRs are handled by csel. + // FIXME: Fold in x+1, -x, and ~x when applicable. + if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || + AArch64::GPR32allRegClass.hasSubClassEq(RC)) { + // Single-cycle csel, csinc, csinv, and csneg. + CondCycles = 1 + ExtraCondLat; + TrueCycles = FalseCycles = 1; + if (canFoldIntoCSel(MRI, TrueReg)) + TrueCycles = 0; + else if (canFoldIntoCSel(MRI, FalseReg)) + FalseCycles = 0; + return true; + } + + // Scalar floating point is handled by fcsel. + // FIXME: Form fabs, fmin, and fmax when applicable. + if (AArch64::FPR64RegClass.hasSubClassEq(RC) || + AArch64::FPR32RegClass.hasSubClassEq(RC)) { + CondCycles = 5 + ExtraCondLat; + TrueCycles = FalseCycles = 2; + return true; + } + + // Can't do vectors. + return false; +} + +void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DstReg, + const SmallVectorImpl &Cond, + unsigned TrueReg, unsigned FalseReg) const { + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + + // Parse the condition code, see parseCondBranch() above. + AArch64CC::CondCode CC; + switch (Cond.size()) { + default: + llvm_unreachable("Unknown condition opcode in Cond"); + case 1: // b.cc + CC = AArch64CC::CondCode(Cond[0].getImm()); + break; + case 3: { // cbz/cbnz + // We must insert a compare against 0. + bool Is64Bit; + switch (Cond[1].getImm()) { + default: + llvm_unreachable("Unknown branch opcode in Cond"); + case AArch64::CBZW: + Is64Bit = 0; + CC = AArch64CC::EQ; + break; + case AArch64::CBZX: + Is64Bit = 1; + CC = AArch64CC::EQ; + break; + case AArch64::CBNZW: + Is64Bit = 0; + CC = AArch64CC::NE; + break; + case AArch64::CBNZX: + Is64Bit = 1; + CC = AArch64CC::NE; + break; + } + unsigned SrcReg = Cond[2].getReg(); + if (Is64Bit) { + // cmp reg, #0 is actually subs xzr, reg, #0. + MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); + BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR) + .addReg(SrcReg) + .addImm(0) + .addImm(0); + } else { + MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); + BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR) + .addReg(SrcReg) + .addImm(0) + .addImm(0); + } + break; + } + case 4: { // tbz/tbnz + // We must insert a tst instruction. + switch (Cond[1].getImm()) { + default: + llvm_unreachable("Unknown branch opcode in Cond"); + case AArch64::TBZW: + case AArch64::TBZX: + CC = AArch64CC::EQ; + break; + case AArch64::TBNZW: + case AArch64::TBNZX: + CC = AArch64CC::NE; + break; + } + // cmp reg, #foo is actually ands xzr, reg, #1<isAsCheapAsAMove(); + + switch (MI->getOpcode()) { + default: + return false; + + // add/sub on register without shift + case AArch64::ADDWri: + case AArch64::ADDXri: + case AArch64::SUBWri: + case AArch64::SUBXri: + return (MI->getOperand(3).getImm() == 0); + + // logical ops on immediate + case AArch64::ANDWri: + case AArch64::ANDXri: + case AArch64::EORWri: + case AArch64::EORXri: + case AArch64::ORRWri: + case AArch64::ORRXri: + return true; + + // logical ops on register without shift + case AArch64::ANDWrr: + case AArch64::ANDXrr: + case AArch64::BICWrr: + case AArch64::BICXrr: + case AArch64::EONWrr: + case AArch64::EONXrr: + case AArch64::EORWrr: + case AArch64::EORXrr: + case AArch64::ORNWrr: + case AArch64::ORNXrr: + case AArch64::ORRWrr: + case AArch64::ORRXrr: + return true; + } + + llvm_unreachable("Unknown opcode to check as cheap as a move!"); +} + +bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SubIdx) const { + switch (MI.getOpcode()) { + default: + return false; + case AArch64::SBFMXri: // aka sxtw + case AArch64::UBFMXri: // aka uxtw + // Check for the 32 -> 64 bit extension case, these instructions can do + // much more. + if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31) + return false; + // This is a signed or unsigned 32 -> 64 bit extension. + SrcReg = MI.getOperand(1).getReg(); + DstReg = MI.getOperand(0).getReg(); + SubIdx = AArch64::sub_32; + return true; + } +} + +bool +AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, + MachineInstr *MIb, + AliasAnalysis *AA) const { + const TargetRegisterInfo *TRI = &getRegisterInfo(); + unsigned BaseRegA = 0, BaseRegB = 0; + int OffsetA = 0, OffsetB = 0; + int WidthA = 0, WidthB = 0; + + assert(MIa && (MIa->mayLoad() || MIa->mayStore()) && + "MIa must be a store or a load"); + assert(MIb && (MIb->mayLoad() || MIb->mayStore()) && + "MIb must be a store or a load"); + + if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() || + MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) + return false; + + // Retrieve the base register, offset from the base register and width. Width + // is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8). If + // base registers are identical, and the offset of a lower memory access + + // the width doesn't overlap the offset of a higher memory access, + // then the memory accesses are different. + if (getLdStBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && + getLdStBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { + if (BaseRegA == BaseRegB) { + int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB; + int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA; + int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; + if (LowOffset + LowWidth <= HighOffset) + return true; + } + } + return false; +} + +/// analyzeCompare - For a comparison instruction, return the source registers +/// in SrcReg and SrcReg2, and the value it compares against in CmpValue. +/// Return true if the comparison instruction can be analyzed. +bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, + unsigned &SrcReg2, int &CmpMask, + int &CmpValue) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::SUBSWrr: + case AArch64::SUBSWrs: + case AArch64::SUBSWrx: + case AArch64::SUBSXrr: + case AArch64::SUBSXrs: + case AArch64::SUBSXrx: + case AArch64::ADDSWrr: + case AArch64::ADDSWrs: + case AArch64::ADDSWrx: + case AArch64::ADDSXrr: + case AArch64::ADDSXrs: + case AArch64::ADDSXrx: + // Replace SUBSWrr with SUBWrr if NZCV is not used. + SrcReg = MI->getOperand(1).getReg(); + SrcReg2 = MI->getOperand(2).getReg(); + CmpMask = ~0; + CmpValue = 0; + return true; + case AArch64::SUBSWri: + case AArch64::ADDSWri: + case AArch64::SUBSXri: + case AArch64::ADDSXri: + SrcReg = MI->getOperand(1).getReg(); + SrcReg2 = 0; + CmpMask = ~0; + // FIXME: In order to convert CmpValue to 0 or 1 + CmpValue = (MI->getOperand(2).getImm() != 0); + return true; + case AArch64::ANDSWri: + case AArch64::ANDSXri: + // ANDS does not use the same encoding scheme as the others xxxS + // instructions. + SrcReg = MI->getOperand(1).getReg(); + SrcReg2 = 0; + CmpMask = ~0; + // FIXME:The return val type of decodeLogicalImmediate is uint64_t, + // while the type of CmpValue is int. When converting uint64_t to int, + // the high 32 bits of uint64_t will be lost. + // In fact it causes a bug in spec2006-483.xalancbmk + // CmpValue is only used to compare with zero in OptimizeCompareInstr + CmpValue = (AArch64_AM::decodeLogicalImmediate( + MI->getOperand(2).getImm(), + MI->getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0); + return true; + } + + return false; +} + +static bool UpdateOperandRegClass(MachineInstr *Instr) { + MachineBasicBlock *MBB = Instr->getParent(); + assert(MBB && "Can't get MachineBasicBlock here"); + MachineFunction *MF = MBB->getParent(); + assert(MF && "Can't get MachineFunction here"); + const TargetMachine *TM = &MF->getTarget(); + const TargetInstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo(); + const TargetRegisterInfo *TRI = TM->getSubtargetImpl()->getRegisterInfo(); + MachineRegisterInfo *MRI = &MF->getRegInfo(); + + for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx; + ++OpIdx) { + MachineOperand &MO = Instr->getOperand(OpIdx); + const TargetRegisterClass *OpRegCstraints = + Instr->getRegClassConstraint(OpIdx, TII, TRI); + + // If there's no constraint, there's nothing to do. + if (!OpRegCstraints) + continue; + // If the operand is a frame index, there's nothing to do here. + // A frame index operand will resolve correctly during PEI. + if (MO.isFI()) + continue; + + assert(MO.isReg() && + "Operand has register constraints without being a register!"); + + unsigned Reg = MO.getReg(); + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { + if (!OpRegCstraints->contains(Reg)) + return false; + } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && + !MRI->constrainRegClass(Reg, OpRegCstraints)) + return false; + } + + return true; +} + +/// \brief Return the opcode that does not set flags when possible - otherwise +/// return the original opcode. The caller is responsible to do the actual +/// substitution and legality checking. +static unsigned convertFlagSettingOpcode(const MachineInstr *MI) { + // Don't convert all compare instructions, because for some the zero register + // encoding becomes the sp register. + bool MIDefinesZeroReg = false; + if (MI->definesRegister(AArch64::WZR) || MI->definesRegister(AArch64::XZR)) + MIDefinesZeroReg = true; + + switch (MI->getOpcode()) { + default: + return MI->getOpcode(); + case AArch64::ADDSWrr: + return AArch64::ADDWrr; + case AArch64::ADDSWri: + return MIDefinesZeroReg ? AArch64::ADDSWri : AArch64::ADDWri; + case AArch64::ADDSWrs: + return MIDefinesZeroReg ? AArch64::ADDSWrs : AArch64::ADDWrs; + case AArch64::ADDSWrx: + return AArch64::ADDWrx; + case AArch64::ADDSXrr: + return AArch64::ADDXrr; + case AArch64::ADDSXri: + return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri; + case AArch64::ADDSXrs: + return MIDefinesZeroReg ? AArch64::ADDSXrs : AArch64::ADDXrs; + case AArch64::ADDSXrx: + return AArch64::ADDXrx; + case AArch64::SUBSWrr: + return AArch64::SUBWrr; + case AArch64::SUBSWri: + return MIDefinesZeroReg ? AArch64::SUBSWri : AArch64::SUBWri; + case AArch64::SUBSWrs: + return MIDefinesZeroReg ? AArch64::SUBSWrs : AArch64::SUBWrs; + case AArch64::SUBSWrx: + return AArch64::SUBWrx; + case AArch64::SUBSXrr: + return AArch64::SUBXrr; + case AArch64::SUBSXri: + return MIDefinesZeroReg ? AArch64::SUBSXri : AArch64::SUBXri; + case AArch64::SUBSXrs: + return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs; + case AArch64::SUBSXrx: + return AArch64::SUBXrx; + } +} + +/// True when condition code could be modified on the instruction +/// trace starting at from and ending at to. +static bool modifiesConditionCode(MachineInstr *From, MachineInstr *To, + const bool CheckOnlyCCWrites, + const TargetRegisterInfo *TRI) { + // We iterate backward starting \p To until we hit \p From + MachineBasicBlock::iterator I = To, E = From, B = To->getParent()->begin(); + + // Early exit if To is at the beginning of the BB. + if (I == B) + return true; + + // Check whether the definition of SrcReg is in the same basic block as + // Compare. If not, assume the condition code gets modified on some path. + if (To->getParent() != From->getParent()) + return true; + + // Check that NZCV isn't set on the trace. + for (--I; I != E; --I) { + const MachineInstr &Instr = *I; + + if (Instr.modifiesRegister(AArch64::NZCV, TRI) || + (!CheckOnlyCCWrites && Instr.readsRegister(AArch64::NZCV, TRI))) + // This instruction modifies or uses NZCV after the one we want to + // change. + return true; + if (I == B) + // We currently don't allow the instruction trace to cross basic + // block boundaries + return true; + } + return false; +} +/// optimizeCompareInstr - Convert the instruction supplying the argument to the +/// comparison into one that sets the zero bit in the flags register. +bool AArch64InstrInfo::optimizeCompareInstr( + MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, + int CmpValue, const MachineRegisterInfo *MRI) const { + + // Replace SUBSWrr with SUBWrr if NZCV is not used. + int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true); + if (Cmp_NZCV != -1) { + if (CmpInstr->definesRegister(AArch64::WZR) || + CmpInstr->definesRegister(AArch64::XZR)) { + CmpInstr->eraseFromParent(); + return true; + } + unsigned Opc = CmpInstr->getOpcode(); + unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); + if (NewOpc == Opc) + return false; + const MCInstrDesc &MCID = get(NewOpc); + CmpInstr->setDesc(MCID); + CmpInstr->RemoveOperand(Cmp_NZCV); + bool succeeded = UpdateOperandRegClass(CmpInstr); + (void)succeeded; + assert(succeeded && "Some operands reg class are incompatible!"); + return true; + } + + // Continue only if we have a "ri" where immediate is zero. + // FIXME:CmpValue has already been converted to 0 or 1 in analyzeCompare + // function. + assert((CmpValue == 0 || CmpValue == 1) && "CmpValue must be 0 or 1!"); + if (CmpValue != 0 || SrcReg2 != 0) + return false; + + // CmpInstr is a Compare instruction if destination register is not used. + if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) + return false; + + // Get the unique definition of SrcReg. + MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); + if (!MI) + return false; + + bool CheckOnlyCCWrites = false; + const TargetRegisterInfo *TRI = &getRegisterInfo(); + if (modifiesConditionCode(MI, CmpInstr, CheckOnlyCCWrites, TRI)) + return false; + + unsigned NewOpc = MI->getOpcode(); + switch (MI->getOpcode()) { + default: + return false; + case AArch64::ADDSWrr: + case AArch64::ADDSWri: + case AArch64::ADDSXrr: + case AArch64::ADDSXri: + case AArch64::SUBSWrr: + case AArch64::SUBSWri: + case AArch64::SUBSXrr: + case AArch64::SUBSXri: + break; + case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break; + case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break; + case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break; + case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break; + case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break; + case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break; + case AArch64::SUBWrr: NewOpc = AArch64::SUBSWrr; break; + case AArch64::SUBWri: NewOpc = AArch64::SUBSWri; break; + case AArch64::SUBXrr: NewOpc = AArch64::SUBSXrr; break; + case AArch64::SUBXri: NewOpc = AArch64::SUBSXri; break; + case AArch64::SBCWr: NewOpc = AArch64::SBCSWr; break; + case AArch64::SBCXr: NewOpc = AArch64::SBCSXr; break; + case AArch64::ANDWri: NewOpc = AArch64::ANDSWri; break; + case AArch64::ANDXri: NewOpc = AArch64::ANDSXri; break; + } + + // Scan forward for the use of NZCV. + // When checking against MI: if it's a conditional code requires + // checking of V bit, then this is not safe to do. + // It is safe to remove CmpInstr if NZCV is redefined or killed. + // If we are done with the basic block, we need to check whether NZCV is + // live-out. + bool IsSafe = false; + for (MachineBasicBlock::iterator I = CmpInstr, + E = CmpInstr->getParent()->end(); + !IsSafe && ++I != E;) { + const MachineInstr &Instr = *I; + for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO; + ++IO) { + const MachineOperand &MO = Instr.getOperand(IO); + if (MO.isRegMask() && MO.clobbersPhysReg(AArch64::NZCV)) { + IsSafe = true; + break; + } + if (!MO.isReg() || MO.getReg() != AArch64::NZCV) + continue; + if (MO.isDef()) { + IsSafe = true; + break; + } + + // Decode the condition code. + unsigned Opc = Instr.getOpcode(); + AArch64CC::CondCode CC; + switch (Opc) { + default: + return false; + case AArch64::Bcc: + CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm(); + break; + case AArch64::CSINVWr: + case AArch64::CSINVXr: + case AArch64::CSINCWr: + case AArch64::CSINCXr: + case AArch64::CSELWr: + case AArch64::CSELXr: + case AArch64::CSNEGWr: + case AArch64::CSNEGXr: + case AArch64::FCSELSrrr: + case AArch64::FCSELDrrr: + CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm(); + break; + } + + // It is not safe to remove Compare instruction if Overflow(V) is used. + switch (CC) { + default: + // NZCV can be used multiple times, we should continue. + break; + case AArch64CC::VS: + case AArch64CC::VC: + case AArch64CC::GE: + case AArch64CC::LT: + case AArch64CC::GT: + case AArch64CC::LE: + return false; + } + } + } + + // If NZCV is not killed nor re-defined, we should check whether it is + // live-out. If it is live-out, do not optimize. + if (!IsSafe) { + MachineBasicBlock *ParentBlock = CmpInstr->getParent(); + for (auto *MBB : ParentBlock->successors()) + if (MBB->isLiveIn(AArch64::NZCV)) + return false; + } + + // Update the instruction to set NZCV. + MI->setDesc(get(NewOpc)); + CmpInstr->eraseFromParent(); + bool succeeded = UpdateOperandRegClass(MI); + (void)succeeded; + assert(succeeded && "Some operands reg class are incompatible!"); + MI->addRegisterDefined(AArch64::NZCV, TRI); + return true; +} + +bool +AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { + if (MI->getOpcode() != TargetOpcode::LOAD_STACK_GUARD) + return false; + + MachineBasicBlock &MBB = *MI->getParent(); + DebugLoc DL = MI->getDebugLoc(); + unsigned Reg = MI->getOperand(0).getReg(); + const GlobalValue *GV = + cast((*MI->memoperands_begin())->getValue()); + const TargetMachine &TM = MBB.getParent()->getTarget(); + unsigned char OpFlags = Subtarget.ClassifyGlobalReference(GV, TM); + const unsigned char MO_NC = AArch64II::MO_NC; + + if ((OpFlags & AArch64II::MO_GOT) != 0) { + BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg) + .addGlobalAddress(GV, 0, AArch64II::MO_GOT); + BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg) + .addReg(Reg, RegState::Kill).addImm(0) + .addMemOperand(*MI->memoperands_begin()); + } else if (TM.getCodeModel() == CodeModel::Large) { + BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg) + .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48); + BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg) + .addReg(Reg, RegState::Kill) + .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32); + BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg) + .addReg(Reg, RegState::Kill) + .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16); + BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg) + .addReg(Reg, RegState::Kill) + .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0); + BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg) + .addReg(Reg, RegState::Kill).addImm(0) + .addMemOperand(*MI->memoperands_begin()); + } else { + BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg) + .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE); + unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC; + BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg) + .addReg(Reg, RegState::Kill) + .addGlobalAddress(GV, 0, LoFlags) + .addMemOperand(*MI->memoperands_begin()); + } + + MBB.erase(MI); + + return true; +} + +/// Return true if this is this instruction has a non-zero immediate +bool AArch64InstrInfo::hasShiftedReg(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::ADDSWrs: + case AArch64::ADDSXrs: + case AArch64::ADDWrs: + case AArch64::ADDXrs: + case AArch64::ANDSWrs: + case AArch64::ANDSXrs: + case AArch64::ANDWrs: + case AArch64::ANDXrs: + case AArch64::BICSWrs: + case AArch64::BICSXrs: + case AArch64::BICWrs: + case AArch64::BICXrs: + case AArch64::CRC32Brr: + case AArch64::CRC32CBrr: + case AArch64::CRC32CHrr: + case AArch64::CRC32CWrr: + case AArch64::CRC32CXrr: + case AArch64::CRC32Hrr: + case AArch64::CRC32Wrr: + case AArch64::CRC32Xrr: + case AArch64::EONWrs: + case AArch64::EONXrs: + case AArch64::EORWrs: + case AArch64::EORXrs: + case AArch64::ORNWrs: + case AArch64::ORNXrs: + case AArch64::ORRWrs: + case AArch64::ORRXrs: + case AArch64::SUBSWrs: + case AArch64::SUBSXrs: + case AArch64::SUBWrs: + case AArch64::SUBXrs: + if (MI->getOperand(3).isImm()) { + unsigned val = MI->getOperand(3).getImm(); + return (val != 0); + } + break; + } + return false; +} + +/// Return true if this is this instruction has a non-zero immediate +bool AArch64InstrInfo::hasExtendedReg(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::ADDSWrx: + case AArch64::ADDSXrx: + case AArch64::ADDSXrx64: + case AArch64::ADDWrx: + case AArch64::ADDXrx: + case AArch64::ADDXrx64: + case AArch64::SUBSWrx: + case AArch64::SUBSXrx: + case AArch64::SUBSXrx64: + case AArch64::SUBWrx: + case AArch64::SUBXrx: + case AArch64::SUBXrx64: + if (MI->getOperand(3).isImm()) { + unsigned val = MI->getOperand(3).getImm(); + return (val != 0); + } + break; + } + + return false; +} + +// Return true if this instruction simply sets its single destination register +// to zero. This is equivalent to a register rename of the zero-register. +bool AArch64InstrInfo::isGPRZero(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::MOVZWi: + case AArch64::MOVZXi: // movz Rd, #0 (LSL #0) + if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) { + assert(MI->getDesc().getNumOperands() == 3 && + MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands"); + return true; + } + break; + case AArch64::ANDWri: // and Rd, Rzr, #imm + return MI->getOperand(1).getReg() == AArch64::WZR; + case AArch64::ANDXri: + return MI->getOperand(1).getReg() == AArch64::XZR; + case TargetOpcode::COPY: + return MI->getOperand(1).getReg() == AArch64::WZR; + } + return false; +} + +// Return true if this instruction simply renames a general register without +// modifying bits. +bool AArch64InstrInfo::isGPRCopy(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: + break; + case TargetOpcode::COPY: { + // GPR32 copies will by lowered to ORRXrs + unsigned DstReg = MI->getOperand(0).getReg(); + return (AArch64::GPR32RegClass.contains(DstReg) || + AArch64::GPR64RegClass.contains(DstReg)); + } + case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0) + if (MI->getOperand(1).getReg() == AArch64::XZR) { + assert(MI->getDesc().getNumOperands() == 4 && + MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands"); + return true; + } + break; + case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0) + if (MI->getOperand(2).getImm() == 0) { + assert(MI->getDesc().getNumOperands() == 4 && + MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands"); + return true; + } + break; + } + return false; +} + +// Return true if this instruction simply renames a general register without +// modifying bits. +bool AArch64InstrInfo::isFPRCopy(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: + break; + case TargetOpcode::COPY: { + // FPR64 copies will by lowered to ORR.16b + unsigned DstReg = MI->getOperand(0).getReg(); + return (AArch64::FPR64RegClass.contains(DstReg) || + AArch64::FPR128RegClass.contains(DstReg)); + } + case AArch64::ORRv16i8: + if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { + assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() && + "invalid ORRv16i8 operands"); + return true; + } + break; + } + return false; +} + +unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::LDRWui: + case AArch64::LDRXui: + case AArch64::LDRBui: + case AArch64::LDRHui: + case AArch64::LDRSui: + case AArch64::LDRDui: + case AArch64::LDRQui: + if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() && + MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; + } + + return 0; +} + +unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::STRWui: + case AArch64::STRXui: + case AArch64::STRBui: + case AArch64::STRHui: + case AArch64::STRSui: + case AArch64::STRDui: + case AArch64::STRQui: + if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() && + MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; + } + return 0; +} + +/// Return true if this is load/store scales or extends its register offset. +/// This refers to scaling a dynamic index as opposed to scaled immediates. +/// MI should be a memory op that allows scaled addressing. +bool AArch64InstrInfo::isScaledAddr(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: + break; + case AArch64::LDRBBroW: + case AArch64::LDRBroW: + case AArch64::LDRDroW: + case AArch64::LDRHHroW: + case AArch64::LDRHroW: + case AArch64::LDRQroW: + case AArch64::LDRSBWroW: + case AArch64::LDRSBXroW: + case AArch64::LDRSHWroW: + case AArch64::LDRSHXroW: + case AArch64::LDRSWroW: + case AArch64::LDRSroW: + case AArch64::LDRWroW: + case AArch64::LDRXroW: + case AArch64::STRBBroW: + case AArch64::STRBroW: + case AArch64::STRDroW: + case AArch64::STRHHroW: + case AArch64::STRHroW: + case AArch64::STRQroW: + case AArch64::STRSroW: + case AArch64::STRWroW: + case AArch64::STRXroW: + case AArch64::LDRBBroX: + case AArch64::LDRBroX: + case AArch64::LDRDroX: + case AArch64::LDRHHroX: + case AArch64::LDRHroX: + case AArch64::LDRQroX: + case AArch64::LDRSBWroX: + case AArch64::LDRSBXroX: + case AArch64::LDRSHWroX: + case AArch64::LDRSHXroX: + case AArch64::LDRSWroX: + case AArch64::LDRSroX: + case AArch64::LDRWroX: + case AArch64::LDRXroX: + case AArch64::STRBBroX: + case AArch64::STRBroX: + case AArch64::STRDroX: + case AArch64::STRHHroX: + case AArch64::STRHroX: + case AArch64::STRQroX: + case AArch64::STRSroX: + case AArch64::STRWroX: + case AArch64::STRXroX: + + unsigned Val = MI->getOperand(3).getImm(); + AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); + return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); + } + return false; +} + +/// Check all MachineMemOperands for a hint to suppress pairing. +bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const { + assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) && + "Too many target MO flags"); + for (auto *MM : MI->memoperands()) { + if (MM->getFlags() & + (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) { + return true; + } + } + return false; +} + +/// Set a flag on the first MachineMemOperand to suppress pairing. +void AArch64InstrInfo::suppressLdStPair(MachineInstr *MI) const { + if (MI->memoperands_empty()) + return; + + assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) && + "Too many target MO flags"); + (*MI->memoperands_begin()) + ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit); +} + +bool +AArch64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, + unsigned &Offset, + const TargetRegisterInfo *TRI) const { + switch (LdSt->getOpcode()) { + default: + return false; + case AArch64::STRSui: + case AArch64::STRDui: + case AArch64::STRQui: + case AArch64::STRXui: + case AArch64::STRWui: + case AArch64::LDRSui: + case AArch64::LDRDui: + case AArch64::LDRQui: + case AArch64::LDRXui: + case AArch64::LDRWui: + if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm()) + return false; + BaseReg = LdSt->getOperand(1).getReg(); + MachineFunction &MF = *LdSt->getParent()->getParent(); + unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize(); + Offset = LdSt->getOperand(2).getImm() * Width; + return true; + }; +} + +bool AArch64InstrInfo::getLdStBaseRegImmOfsWidth( + MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width, + const TargetRegisterInfo *TRI) const { + // Handle only loads/stores with base register followed by immediate offset. + if (LdSt->getNumOperands() != 3) + return false; + if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm()) + return false; + + // Offset is calculated as the immediate operand multiplied by the scaling factor. + // Unscaled instructions have scaling factor set to 1. + int Scale = 0; + switch (LdSt->getOpcode()) { + default: + return false; + case AArch64::LDURQi: + case AArch64::STURQi: + Width = 16; + Scale = 1; + break; + case AArch64::LDURXi: + case AArch64::LDURDi: + case AArch64::STURXi: + case AArch64::STURDi: + Width = 8; + Scale = 1; + break; + case AArch64::LDURWi: + case AArch64::LDURSi: + case AArch64::LDURSWi: + case AArch64::STURWi: + case AArch64::STURSi: + Width = 4; + Scale = 1; + break; + case AArch64::LDURHi: + case AArch64::LDURHHi: + case AArch64::LDURSHXi: + case AArch64::LDURSHWi: + case AArch64::STURHi: + case AArch64::STURHHi: + Width = 2; + Scale = 1; + break; + case AArch64::LDURBi: + case AArch64::LDURBBi: + case AArch64::LDURSBXi: + case AArch64::LDURSBWi: + case AArch64::STURBi: + case AArch64::STURBBi: + Width = 1; + Scale = 1; + break; + case AArch64::LDRXui: + case AArch64::STRXui: + Scale = Width = 8; + break; + case AArch64::LDRWui: + case AArch64::STRWui: + Scale = Width = 4; + break; + case AArch64::LDRBui: + case AArch64::STRBui: + Scale = Width = 1; + break; + case AArch64::LDRHui: + case AArch64::STRHui: + Scale = Width = 2; + break; + case AArch64::LDRSui: + case AArch64::STRSui: + Scale = Width = 4; + break; + case AArch64::LDRDui: + case AArch64::STRDui: + Scale = Width = 8; + break; + case AArch64::LDRQui: + case AArch64::STRQui: + Scale = Width = 16; + break; + case AArch64::LDRBBui: + case AArch64::STRBBui: + Scale = Width = 1; + break; + case AArch64::LDRHHui: + case AArch64::STRHHui: + Scale = Width = 2; + break; + }; + + BaseReg = LdSt->getOperand(1).getReg(); + Offset = LdSt->getOperand(2).getImm() * Scale; + return true; +} + +/// Detect opportunities for ldp/stp formation. +/// +/// Only called for LdSt for which getLdStBaseRegImmOfs returns true. +bool AArch64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt, + MachineInstr *SecondLdSt, + unsigned NumLoads) const { + // Only cluster up to a single pair. + if (NumLoads > 1) + return false; + if (FirstLdSt->getOpcode() != SecondLdSt->getOpcode()) + return false; + // getLdStBaseRegImmOfs guarantees that oper 2 isImm. + unsigned Ofs1 = FirstLdSt->getOperand(2).getImm(); + // Allow 6 bits of positive range. + if (Ofs1 > 64) + return false; + // The caller should already have ordered First/SecondLdSt by offset. + unsigned Ofs2 = SecondLdSt->getOperand(2).getImm(); + return Ofs1 + 1 == Ofs2; +} + +bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First, + MachineInstr *Second) const { + // Cyclone can fuse CMN, CMP followed by Bcc. + + // FIXME: B0 can also fuse: + // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ. + if (Second->getOpcode() != AArch64::Bcc) + return false; + switch (First->getOpcode()) { + default: + return false; + case AArch64::SUBSWri: + case AArch64::ADDSWri: + case AArch64::ANDSWri: + case AArch64::SUBSXri: + case AArch64::ADDSXri: + case AArch64::ANDSXri: + return true; + } +} + +MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue( + MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var, + const MDNode *Expr, DebugLoc DL) const { + MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) + .addFrameIndex(FrameIx) + .addImm(0) + .addImm(Offset) + .addMetadata(Var) + .addMetadata(Expr); + return &*MIB; +} + +static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB, + unsigned Reg, unsigned SubIdx, + unsigned State, + const TargetRegisterInfo *TRI) { + if (!SubIdx) + return MIB.addReg(Reg, State); + + if (TargetRegisterInfo::isPhysicalRegister(Reg)) + return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); + return MIB.addReg(Reg, State, SubIdx); +} + +static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, + unsigned NumRegs) { + // We really want the positive remainder mod 32 here, that happens to be + // easily obtainable with a mask. + return ((DestReg - SrcReg) & 0x1f) < NumRegs; +} + +void AArch64InstrInfo::copyPhysRegTuple( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, + llvm::ArrayRef Indices) const { + assert(Subtarget.hasNEON() && + "Unexpected register copy without NEON"); + const TargetRegisterInfo *TRI = &getRegisterInfo(); + uint16_t DestEncoding = TRI->getEncodingValue(DestReg); + uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg); + unsigned NumRegs = Indices.size(); + + int SubReg = 0, End = NumRegs, Incr = 1; + if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) { + SubReg = NumRegs - 1; + End = -1; + Incr = -1; + } + + for (; SubReg != End; SubReg += Incr) { + const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode)); + AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); + AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI); + AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); + } +} + +void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const { + if (AArch64::GPR32spRegClass.contains(DestReg) && + (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) { + const TargetRegisterInfo *TRI = &getRegisterInfo(); + + if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { + // If either operand is WSP, expand to ADD #0. + if (Subtarget.hasZeroCycleRegMove()) { + // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move. + unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, + &AArch64::GPR64spRegClass); + unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32, + &AArch64::GPR64spRegClass); + // This instruction is reading and writing X registers. This may upset + // the register scavenger and machine verifier, so we need to indicate + // that we are reading an undefined value from SrcRegX, but a proper + // value from SrcReg. + BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX) + .addReg(SrcRegX, RegState::Undef) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) + .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); + } else { + BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } + } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) { + BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm( + AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } else { + if (Subtarget.hasZeroCycleRegMove()) { + // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move. + unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, + &AArch64::GPR64spRegClass); + unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32, + &AArch64::GPR64spRegClass); + // This instruction is reading and writing X registers. This may upset + // the register scavenger and machine verifier, so we need to indicate + // that we are reading an undefined value from SrcRegX, but a proper + // value from SrcReg. + BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX) + .addReg(AArch64::XZR) + .addReg(SrcRegX, RegState::Undef) + .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); + } else { + // Otherwise, expand to ORR WZR. + BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg) + .addReg(AArch64::WZR) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + } + return; + } + + if (AArch64::GPR64spRegClass.contains(DestReg) && + (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) { + if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { + // If either operand is SP, expand to ADD #0. + BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) { + BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm( + AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } else { + // Otherwise, expand to ORR XZR. + BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) + .addReg(AArch64::XZR) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + return; + } + + // Copy a DDDD register quad by copying the individual sub-registers. + if (AArch64::DDDDRegClass.contains(DestReg) && + AArch64::DDDDRegClass.contains(SrcReg)) { + static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1, + AArch64::dsub2, AArch64::dsub3 }; + copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, + Indices); + return; + } + + // Copy a DDD register triple by copying the individual sub-registers. + if (AArch64::DDDRegClass.contains(DestReg) && + AArch64::DDDRegClass.contains(SrcReg)) { + static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1, + AArch64::dsub2 }; + copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, + Indices); + return; + } + + // Copy a DD register pair by copying the individual sub-registers. + if (AArch64::DDRegClass.contains(DestReg) && + AArch64::DDRegClass.contains(SrcReg)) { + static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1 }; + copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, + Indices); + return; + } + + // Copy a QQQQ register quad by copying the individual sub-registers. + if (AArch64::QQQQRegClass.contains(DestReg) && + AArch64::QQQQRegClass.contains(SrcReg)) { + static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1, + AArch64::qsub2, AArch64::qsub3 }; + copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, + Indices); + return; + } + + // Copy a QQQ register triple by copying the individual sub-registers. + if (AArch64::QQQRegClass.contains(DestReg) && + AArch64::QQQRegClass.contains(SrcReg)) { + static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1, + AArch64::qsub2 }; + copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, + Indices); + return; + } + + // Copy a QQ register pair by copying the individual sub-registers. + if (AArch64::QQRegClass.contains(DestReg) && + AArch64::QQRegClass.contains(SrcReg)) { + static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1 }; + copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, + Indices); + return; + } + + if (AArch64::FPR128RegClass.contains(DestReg) && + AArch64::FPR128RegClass.contains(SrcReg)) { + if(Subtarget.hasNEON()) { + BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) + .addReg(SrcReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else { + BuildMI(MBB, I, DL, get(AArch64::STRQpre)) + .addReg(AArch64::SP, RegState::Define) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addReg(AArch64::SP) + .addImm(-16); + BuildMI(MBB, I, DL, get(AArch64::LDRQpre)) + .addReg(AArch64::SP, RegState::Define) + .addReg(DestReg, RegState::Define) + .addReg(AArch64::SP) + .addImm(16); + } + return; + } + + if (AArch64::FPR64RegClass.contains(DestReg) && + AArch64::FPR64RegClass.contains(SrcReg)) { + if(Subtarget.hasNEON()) { + DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, + &AArch64::FPR128RegClass); + SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub, + &AArch64::FPR128RegClass); + BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) + .addReg(SrcReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else { + BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + return; + } + + if (AArch64::FPR32RegClass.contains(DestReg) && + AArch64::FPR32RegClass.contains(SrcReg)) { + if(Subtarget.hasNEON()) { + DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, + &AArch64::FPR128RegClass); + SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub, + &AArch64::FPR128RegClass); + BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) + .addReg(SrcReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else { + BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + return; + } + + if (AArch64::FPR16RegClass.contains(DestReg) && + AArch64::FPR16RegClass.contains(SrcReg)) { + if(Subtarget.hasNEON()) { + DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, + &AArch64::FPR128RegClass); + SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, + &AArch64::FPR128RegClass); + BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) + .addReg(SrcReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else { + DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, + &AArch64::FPR32RegClass); + SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, + &AArch64::FPR32RegClass); + BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + return; + } + + if (AArch64::FPR8RegClass.contains(DestReg) && + AArch64::FPR8RegClass.contains(SrcReg)) { + if(Subtarget.hasNEON()) { + DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, + &AArch64::FPR128RegClass); + SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, + &AArch64::FPR128RegClass); + BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) + .addReg(SrcReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else { + DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, + &AArch64::FPR32RegClass); + SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, + &AArch64::FPR32RegClass); + BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + return; + } + + // Copies between GPR64 and FPR64. + if (AArch64::FPR64RegClass.contains(DestReg) && + AArch64::GPR64RegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + if (AArch64::GPR64RegClass.contains(DestReg) && + AArch64::FPR64RegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + // Copies between GPR32 and FPR32. + if (AArch64::FPR32RegClass.contains(DestReg) && + AArch64::GPR32RegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + if (AArch64::GPR32RegClass.contains(DestReg) && + AArch64::FPR32RegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + + if (DestReg == AArch64::NZCV) { + assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); + BuildMI(MBB, I, DL, get(AArch64::MSR)) + .addImm(AArch64SysReg::NZCV) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define); + return; + } + + if (SrcReg == AArch64::NZCV) { + assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); + BuildMI(MBB, I, DL, get(AArch64::MRS)) + .addReg(DestReg) + .addImm(AArch64SysReg::NZCV) + .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc)); + return; + } + + llvm_unreachable("unimplemented reg-to-reg copy"); +} + +void AArch64InstrInfo::storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, + bool isKill, int FI, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (MBBI != MBB.end()) + DL = MBBI->getDebugLoc(); + MachineFunction &MF = *MBB.getParent(); + MachineFrameInfo &MFI = *MF.getFrameInfo(); + unsigned Align = MFI.getObjectAlignment(FI); + + MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI)); + MachineMemOperand *MMO = MF.getMachineMemOperand( + PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align); + unsigned Opc = 0; + bool Offset = true; + switch (RC->getSize()) { + case 1: + if (AArch64::FPR8RegClass.hasSubClassEq(RC)) + Opc = AArch64::STRBui; + break; + case 2: + if (AArch64::FPR16RegClass.hasSubClassEq(RC)) + Opc = AArch64::STRHui; + break; + case 4: + if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { + Opc = AArch64::STRWui; + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) + MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); + else + assert(SrcReg != AArch64::WSP); + } else if (AArch64::FPR32RegClass.hasSubClassEq(RC)) + Opc = AArch64::STRSui; + break; + case 8: + if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) { + Opc = AArch64::STRXui; + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) + MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); + else + assert(SrcReg != AArch64::SP); + } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) + Opc = AArch64::STRDui; + break; + case 16: + if (AArch64::FPR128RegClass.hasSubClassEq(RC)) + Opc = AArch64::STRQui; + else if (AArch64::DDRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register store without NEON"); + Opc = AArch64::ST1Twov1d, Offset = false; + } + break; + case 24: + if (AArch64::DDDRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register store without NEON"); + Opc = AArch64::ST1Threev1d, Offset = false; + } + break; + case 32: + if (AArch64::DDDDRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register store without NEON"); + Opc = AArch64::ST1Fourv1d, Offset = false; + } else if (AArch64::QQRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register store without NEON"); + Opc = AArch64::ST1Twov2d, Offset = false; + } + break; + case 48: + if (AArch64::QQQRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register store without NEON"); + Opc = AArch64::ST1Threev2d, Offset = false; + } + break; + case 64: + if (AArch64::QQQQRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register store without NEON"); + Opc = AArch64::ST1Fourv2d, Offset = false; + } + break; + } + assert(Opc && "Unknown register class"); + + const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc)) + .addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI); + + if (Offset) + MI.addImm(0); + MI.addMemOperand(MMO); +} + +void AArch64InstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, + int FI, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (MBBI != MBB.end()) + DL = MBBI->getDebugLoc(); + MachineFunction &MF = *MBB.getParent(); + MachineFrameInfo &MFI = *MF.getFrameInfo(); + unsigned Align = MFI.getObjectAlignment(FI); + MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI)); + MachineMemOperand *MMO = MF.getMachineMemOperand( + PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align); + + unsigned Opc = 0; + bool Offset = true; + switch (RC->getSize()) { + case 1: + if (AArch64::FPR8RegClass.hasSubClassEq(RC)) + Opc = AArch64::LDRBui; + break; + case 2: + if (AArch64::FPR16RegClass.hasSubClassEq(RC)) + Opc = AArch64::LDRHui; + break; + case 4: + if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { + Opc = AArch64::LDRWui; + if (TargetRegisterInfo::isVirtualRegister(DestReg)) + MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); + else + assert(DestReg != AArch64::WSP); + } else if (AArch64::FPR32RegClass.hasSubClassEq(RC)) + Opc = AArch64::LDRSui; + break; + case 8: + if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) { + Opc = AArch64::LDRXui; + if (TargetRegisterInfo::isVirtualRegister(DestReg)) + MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); + else + assert(DestReg != AArch64::SP); + } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) + Opc = AArch64::LDRDui; + break; + case 16: + if (AArch64::FPR128RegClass.hasSubClassEq(RC)) + Opc = AArch64::LDRQui; + else if (AArch64::DDRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register load without NEON"); + Opc = AArch64::LD1Twov1d, Offset = false; + } + break; + case 24: + if (AArch64::DDDRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register load without NEON"); + Opc = AArch64::LD1Threev1d, Offset = false; + } + break; + case 32: + if (AArch64::DDDDRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register load without NEON"); + Opc = AArch64::LD1Fourv1d, Offset = false; + } else if (AArch64::QQRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register load without NEON"); + Opc = AArch64::LD1Twov2d, Offset = false; + } + break; + case 48: + if (AArch64::QQQRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register load without NEON"); + Opc = AArch64::LD1Threev2d, Offset = false; + } + break; + case 64: + if (AArch64::QQQQRegClass.hasSubClassEq(RC)) { + assert(Subtarget.hasNEON() && + "Unexpected register load without NEON"); + Opc = AArch64::LD1Fourv2d, Offset = false; + } + break; + } + assert(Opc && "Unknown register class"); + + const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc)) + .addReg(DestReg, getDefRegState(true)) + .addFrameIndex(FI); + if (Offset) + MI.addImm(0); + MI.addMemOperand(MMO); +} + +void llvm::emitFrameOffset(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, int Offset, + const TargetInstrInfo *TII, + MachineInstr::MIFlag Flag, bool SetNZCV) { + if (DestReg == SrcReg && Offset == 0) + return; + + bool isSub = Offset < 0; + if (isSub) + Offset = -Offset; + + // FIXME: If the offset won't fit in 24-bits, compute the offset into a + // scratch register. If DestReg is a virtual register, use it as the + // scratch register; otherwise, create a new virtual register (to be + // replaced by the scavenger at the end of PEI). That case can be optimized + // slightly if DestReg is SP which is always 16-byte aligned, so the scratch + // register can be loaded with offset%8 and the add/sub can use an extending + // instruction with LSL#3. + // Currently the function handles any offsets but generates a poor sequence + // of code. + // assert(Offset < (1 << 24) && "unimplemented reg plus immediate"); + + unsigned Opc; + if (SetNZCV) + Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri; + else + Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri; + const unsigned MaxEncoding = 0xfff; + const unsigned ShiftSize = 12; + const unsigned MaxEncodableValue = MaxEncoding << ShiftSize; + while (((unsigned)Offset) >= (1 << ShiftSize)) { + unsigned ThisVal; + if (((unsigned)Offset) > MaxEncodableValue) { + ThisVal = MaxEncodableValue; + } else { + ThisVal = Offset & MaxEncodableValue; + } + assert((ThisVal >> ShiftSize) <= MaxEncoding && + "Encoding cannot handle value that big"); + BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) + .addReg(SrcReg) + .addImm(ThisVal >> ShiftSize) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftSize)) + .setMIFlag(Flag); + + SrcReg = DestReg; + Offset -= ThisVal; + if (Offset == 0) + return; + } + BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) + .addReg(SrcReg) + .addImm(Offset) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) + .setMIFlag(Flag); +} + +MachineInstr * +AArch64InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, + const SmallVectorImpl &Ops, + int FrameIndex) const { + // This is a bit of a hack. Consider this instruction: + // + // %vreg0 = COPY %SP; GPR64all:%vreg0 + // + // We explicitly chose GPR64all for the virtual register so such a copy might + // be eliminated by RegisterCoalescer. However, that may not be possible, and + // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all + // register class, TargetInstrInfo::foldMemoryOperand() is going to try. + // + // To prevent that, we are going to constrain the %vreg0 register class here. + // + // + // + if (MI->isCopy()) { + unsigned DstReg = MI->getOperand(0).getReg(); + unsigned SrcReg = MI->getOperand(1).getReg(); + if (SrcReg == AArch64::SP && + TargetRegisterInfo::isVirtualRegister(DstReg)) { + MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); + return nullptr; + } + if (DstReg == AArch64::SP && + TargetRegisterInfo::isVirtualRegister(SrcReg)) { + MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); + return nullptr; + } + } + + // Cannot fold. + return nullptr; +} + +int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, + bool *OutUseUnscaledOp, + unsigned *OutUnscaledOp, + int *EmittableOffset) { + int Scale = 1; + bool IsSigned = false; + // The ImmIdx should be changed case by case if it is not 2. + unsigned ImmIdx = 2; + unsigned UnscaledOp = 0; + // Set output values in case of early exit. + if (EmittableOffset) + *EmittableOffset = 0; + if (OutUseUnscaledOp) + *OutUseUnscaledOp = false; + if (OutUnscaledOp) + *OutUnscaledOp = 0; + switch (MI.getOpcode()) { + default: + llvm_unreachable("unhandled opcode in rewriteAArch64FrameIndex"); + // Vector spills/fills can't take an immediate offset. + case AArch64::LD1Twov2d: + case AArch64::LD1Threev2d: + case AArch64::LD1Fourv2d: + case AArch64::LD1Twov1d: + case AArch64::LD1Threev1d: + case AArch64::LD1Fourv1d: + case AArch64::ST1Twov2d: + case AArch64::ST1Threev2d: + case AArch64::ST1Fourv2d: + case AArch64::ST1Twov1d: + case AArch64::ST1Threev1d: + case AArch64::ST1Fourv1d: + return AArch64FrameOffsetCannotUpdate; + case AArch64::PRFMui: + Scale = 8; + UnscaledOp = AArch64::PRFUMi; + break; + case AArch64::LDRXui: + Scale = 8; + UnscaledOp = AArch64::LDURXi; + break; + case AArch64::LDRWui: + Scale = 4; + UnscaledOp = AArch64::LDURWi; + break; + case AArch64::LDRBui: + Scale = 1; + UnscaledOp = AArch64::LDURBi; + break; + case AArch64::LDRHui: + Scale = 2; + UnscaledOp = AArch64::LDURHi; + break; + case AArch64::LDRSui: + Scale = 4; + UnscaledOp = AArch64::LDURSi; + break; + case AArch64::LDRDui: + Scale = 8; + UnscaledOp = AArch64::LDURDi; + break; + case AArch64::LDRQui: + Scale = 16; + UnscaledOp = AArch64::LDURQi; + break; + case AArch64::LDRBBui: + Scale = 1; + UnscaledOp = AArch64::LDURBBi; + break; + case AArch64::LDRHHui: + Scale = 2; + UnscaledOp = AArch64::LDURHHi; + break; + case AArch64::LDRSBXui: + Scale = 1; + UnscaledOp = AArch64::LDURSBXi; + break; + case AArch64::LDRSBWui: + Scale = 1; + UnscaledOp = AArch64::LDURSBWi; + break; + case AArch64::LDRSHXui: + Scale = 2; + UnscaledOp = AArch64::LDURSHXi; + break; + case AArch64::LDRSHWui: + Scale = 2; + UnscaledOp = AArch64::LDURSHWi; + break; + case AArch64::LDRSWui: + Scale = 4; + UnscaledOp = AArch64::LDURSWi; + break; + + case AArch64::STRXui: + Scale = 8; + UnscaledOp = AArch64::STURXi; + break; + case AArch64::STRWui: + Scale = 4; + UnscaledOp = AArch64::STURWi; + break; + case AArch64::STRBui: + Scale = 1; + UnscaledOp = AArch64::STURBi; + break; + case AArch64::STRHui: + Scale = 2; + UnscaledOp = AArch64::STURHi; + break; + case AArch64::STRSui: + Scale = 4; + UnscaledOp = AArch64::STURSi; + break; + case AArch64::STRDui: + Scale = 8; + UnscaledOp = AArch64::STURDi; + break; + case AArch64::STRQui: + Scale = 16; + UnscaledOp = AArch64::STURQi; + break; + case AArch64::STRBBui: + Scale = 1; + UnscaledOp = AArch64::STURBBi; + break; + case AArch64::STRHHui: + Scale = 2; + UnscaledOp = AArch64::STURHHi; + break; + + case AArch64::LDPXi: + case AArch64::LDPDi: + case AArch64::STPXi: + case AArch64::STPDi: + IsSigned = true; + Scale = 8; + break; + case AArch64::LDPQi: + case AArch64::STPQi: + IsSigned = true; + Scale = 16; + break; + case AArch64::LDPWi: + case AArch64::LDPSi: + case AArch64::STPWi: + case AArch64::STPSi: + IsSigned = true; + Scale = 4; + break; + + case AArch64::LDURXi: + case AArch64::LDURWi: + case AArch64::LDURBi: + case AArch64::LDURHi: + case AArch64::LDURSi: + case AArch64::LDURDi: + case AArch64::LDURQi: + case AArch64::LDURHHi: + case AArch64::LDURBBi: + case AArch64::LDURSBXi: + case AArch64::LDURSBWi: + case AArch64::LDURSHXi: + case AArch64::LDURSHWi: + case AArch64::LDURSWi: + case AArch64::STURXi: + case AArch64::STURWi: + case AArch64::STURBi: + case AArch64::STURHi: + case AArch64::STURSi: + case AArch64::STURDi: + case AArch64::STURQi: + case AArch64::STURBBi: + case AArch64::STURHHi: + Scale = 1; + break; + } + + Offset += MI.getOperand(ImmIdx).getImm() * Scale; + + bool useUnscaledOp = false; + // If the offset doesn't match the scale, we rewrite the instruction to + // use the unscaled instruction instead. Likewise, if we have a negative + // offset (and have an unscaled op to use). + if ((Offset & (Scale - 1)) != 0 || (Offset < 0 && UnscaledOp != 0)) + useUnscaledOp = true; + + // Use an unscaled addressing mode if the instruction has a negative offset + // (or if the instruction is already using an unscaled addressing mode). + unsigned MaskBits; + if (IsSigned) { + // ldp/stp instructions. + MaskBits = 7; + Offset /= Scale; + } else if (UnscaledOp == 0 || useUnscaledOp) { + MaskBits = 9; + IsSigned = true; + Scale = 1; + } else { + MaskBits = 12; + IsSigned = false; + Offset /= Scale; + } + + // Attempt to fold address computation. + int MaxOff = (1 << (MaskBits - IsSigned)) - 1; + int MinOff = (IsSigned ? (-MaxOff - 1) : 0); + if (Offset >= MinOff && Offset <= MaxOff) { + if (EmittableOffset) + *EmittableOffset = Offset; + Offset = 0; + } else { + int NewOff = Offset < 0 ? MinOff : MaxOff; + if (EmittableOffset) + *EmittableOffset = NewOff; + Offset = (Offset - NewOff) * Scale; + } + if (OutUseUnscaledOp) + *OutUseUnscaledOp = useUnscaledOp; + if (OutUnscaledOp) + *OutUnscaledOp = UnscaledOp; + return AArch64FrameOffsetCanUpdate | + (Offset == 0 ? AArch64FrameOffsetIsLegal : 0); +} + +bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned FrameReg, int &Offset, + const AArch64InstrInfo *TII) { + unsigned Opcode = MI.getOpcode(); + unsigned ImmIdx = FrameRegIdx + 1; + + if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) { + Offset += MI.getOperand(ImmIdx).getImm(); + emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(), + MI.getOperand(0).getReg(), FrameReg, Offset, TII, + MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri)); + MI.eraseFromParent(); + Offset = 0; + return true; + } + + int NewOffset; + unsigned UnscaledOp; + bool UseUnscaledOp; + int Status = isAArch64FrameOffsetLegal(MI, Offset, &UseUnscaledOp, + &UnscaledOp, &NewOffset); + if (Status & AArch64FrameOffsetCanUpdate) { + if (Status & AArch64FrameOffsetIsLegal) + // Replace the FrameIndex with FrameReg. + MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); + if (UseUnscaledOp) + MI.setDesc(TII->get(UnscaledOp)); + + MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset); + return Offset == 0; + } + + return false; +} + +void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { + NopInst.setOpcode(AArch64::HINT); + NopInst.addOperand(MCOperand::CreateImm(0)); +} +/// useMachineCombiner - return true when a target supports MachineCombiner +bool AArch64InstrInfo::useMachineCombiner() const { + // AArch64 supports the combiner + return true; +} +// +// True when Opc sets flag +static bool isCombineInstrSettingFlag(unsigned Opc) { + switch (Opc) { + case AArch64::ADDSWrr: + case AArch64::ADDSWri: + case AArch64::ADDSXrr: + case AArch64::ADDSXri: + case AArch64::SUBSWrr: + case AArch64::SUBSXrr: + // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi. + case AArch64::SUBSWri: + case AArch64::SUBSXri: + return true; + default: + break; + } + return false; +} +// +// 32b Opcodes that can be combined with a MUL +static bool isCombineInstrCandidate32(unsigned Opc) { + switch (Opc) { + case AArch64::ADDWrr: + case AArch64::ADDWri: + case AArch64::SUBWrr: + case AArch64::ADDSWrr: + case AArch64::ADDSWri: + case AArch64::SUBSWrr: + // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi. + case AArch64::SUBWri: + case AArch64::SUBSWri: + return true; + default: + break; + } + return false; +} +// +// 64b Opcodes that can be combined with a MUL +static bool isCombineInstrCandidate64(unsigned Opc) { + switch (Opc) { + case AArch64::ADDXrr: + case AArch64::ADDXri: + case AArch64::SUBXrr: + case AArch64::ADDSXrr: + case AArch64::ADDSXri: + case AArch64::SUBSXrr: + // Note: MSUB Wd,Wn,Wm,Wi -> Wd = Wi - WnxWm, not Wd=WnxWm - Wi. + case AArch64::SUBXri: + case AArch64::SUBSXri: + return true; + default: + break; + } + return false; +} +// +// Opcodes that can be combined with a MUL +static bool isCombineInstrCandidate(unsigned Opc) { + return (isCombineInstrCandidate32(Opc) || isCombineInstrCandidate64(Opc)); +} + +static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO, + unsigned MulOpc, unsigned ZeroReg) { + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + MachineInstr *MI = nullptr; + // We need a virtual register definition. + if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) + MI = MRI.getUniqueVRegDef(MO.getReg()); + // And it needs to be in the trace (otherwise, it won't have a depth). + if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != MulOpc) + return false; + + assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() && + MI->getOperand(1).isReg() && MI->getOperand(2).isReg() && + MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs"); + + // The third input reg must be zero. + if (MI->getOperand(3).getReg() != ZeroReg) + return false; + + // Must only used by the user we combine with. + if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg())) + return false; + + return true; +} + +/// hasPattern - return true when there is potentially a faster code sequence +/// for an instruction chain ending in \p Root. All potential patterns are +/// listed +/// in the \p Pattern vector. Pattern should be sorted in priority order since +/// the pattern evaluator stops checking as soon as it finds a faster sequence. + +bool AArch64InstrInfo::hasPattern( + MachineInstr &Root, + SmallVectorImpl &Pattern) const { + unsigned Opc = Root.getOpcode(); + MachineBasicBlock &MBB = *Root.getParent(); + bool Found = false; + + if (!isCombineInstrCandidate(Opc)) + return 0; + if (isCombineInstrSettingFlag(Opc)) { + int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); + // When NZCV is live bail out. + if (Cmp_NZCV == -1) + return 0; + unsigned NewOpc = convertFlagSettingOpcode(&Root); + // When opcode can't change bail out. + // CHECKME: do we miss any cases for opcode conversion? + if (NewOpc == Opc) + return 0; + Opc = NewOpc; + } + + switch (Opc) { + default: + break; + case AArch64::ADDWrr: + assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() && + "ADDWrr does not have register operands"); + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, + AArch64::WZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULADDW_OP1); + Found = true; + } + if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr, + AArch64::WZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULADDW_OP2); + Found = true; + } + break; + case AArch64::ADDXrr: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, + AArch64::XZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULADDX_OP1); + Found = true; + } + if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr, + AArch64::XZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULADDX_OP2); + Found = true; + } + break; + case AArch64::SUBWrr: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, + AArch64::WZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULSUBW_OP1); + Found = true; + } + if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr, + AArch64::WZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULSUBW_OP2); + Found = true; + } + break; + case AArch64::SUBXrr: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, + AArch64::XZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULSUBX_OP1); + Found = true; + } + if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr, + AArch64::XZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULSUBX_OP2); + Found = true; + } + break; + case AArch64::ADDWri: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, + AArch64::WZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULADDWI_OP1); + Found = true; + } + break; + case AArch64::ADDXri: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, + AArch64::XZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULADDXI_OP1); + Found = true; + } + break; + case AArch64::SUBWri: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, + AArch64::WZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULSUBWI_OP1); + Found = true; + } + break; + case AArch64::SUBXri: + if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, + AArch64::XZR)) { + Pattern.push_back(MachineCombinerPattern::MC_MULSUBXI_OP1); + Found = true; + } + break; + } + return Found; +} + +/// genMadd - Generate madd instruction and combine mul and add. +/// Example: +/// MUL I=A,B,0 +/// ADD R,I,C +/// ==> MADD R,A,B,C +/// \param Root is the ADD instruction +/// \param [out] InsInstrs is a vector of machine instructions and will +/// contain the generated madd instruction +/// \param IdxMulOpd is index of operand in Root that is the result of +/// the MUL. In the example above IdxMulOpd is 1. +/// \param MaddOpc the opcode fo the madd instruction +static MachineInstr *genMadd(MachineFunction &MF, MachineRegisterInfo &MRI, + const TargetInstrInfo *TII, MachineInstr &Root, + SmallVectorImpl &InsInstrs, + unsigned IdxMulOpd, unsigned MaddOpc, + const TargetRegisterClass *RC) { + assert(IdxMulOpd == 1 || IdxMulOpd == 2); + + unsigned IdxOtherOpd = IdxMulOpd == 1 ? 2 : 1; + MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); + unsigned ResultReg = Root.getOperand(0).getReg(); + unsigned SrcReg0 = MUL->getOperand(1).getReg(); + bool Src0IsKill = MUL->getOperand(1).isKill(); + unsigned SrcReg1 = MUL->getOperand(2).getReg(); + bool Src1IsKill = MUL->getOperand(2).isKill(); + unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); + bool Src2IsKill = Root.getOperand(IdxOtherOpd).isKill(); + + if (TargetRegisterInfo::isVirtualRegister(ResultReg)) + MRI.constrainRegClass(ResultReg, RC); + if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) + MRI.constrainRegClass(SrcReg0, RC); + if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) + MRI.constrainRegClass(SrcReg1, RC); + if (TargetRegisterInfo::isVirtualRegister(SrcReg2)) + MRI.constrainRegClass(SrcReg2, RC); + + MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), + ResultReg) + .addReg(SrcReg0, getKillRegState(Src0IsKill)) + .addReg(SrcReg1, getKillRegState(Src1IsKill)) + .addReg(SrcReg2, getKillRegState(Src2IsKill)); + // Insert the MADD + InsInstrs.push_back(MIB); + return MUL; +} + +/// genMaddR - Generate madd instruction and combine mul and add using +/// an extra virtual register +/// Example - an ADD intermediate needs to be stored in a register: +/// MUL I=A,B,0 +/// ADD R,I,Imm +/// ==> ORR V, ZR, Imm +/// ==> MADD R,A,B,V +/// \param Root is the ADD instruction +/// \param [out] InsInstrs is a vector of machine instructions and will +/// contain the generated madd instruction +/// \param IdxMulOpd is index of operand in Root that is the result of +/// the MUL. In the example above IdxMulOpd is 1. +/// \param MaddOpc the opcode fo the madd instruction +/// \param VR is a virtual register that holds the value of an ADD operand +/// (V in the example above). +static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI, + const TargetInstrInfo *TII, MachineInstr &Root, + SmallVectorImpl &InsInstrs, + unsigned IdxMulOpd, unsigned MaddOpc, + unsigned VR, const TargetRegisterClass *RC) { + assert(IdxMulOpd == 1 || IdxMulOpd == 2); + + MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); + unsigned ResultReg = Root.getOperand(0).getReg(); + unsigned SrcReg0 = MUL->getOperand(1).getReg(); + bool Src0IsKill = MUL->getOperand(1).isKill(); + unsigned SrcReg1 = MUL->getOperand(2).getReg(); + bool Src1IsKill = MUL->getOperand(2).isKill(); + + if (TargetRegisterInfo::isVirtualRegister(ResultReg)) + MRI.constrainRegClass(ResultReg, RC); + if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) + MRI.constrainRegClass(SrcReg0, RC); + if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) + MRI.constrainRegClass(SrcReg1, RC); + if (TargetRegisterInfo::isVirtualRegister(VR)) + MRI.constrainRegClass(VR, RC); + + MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), + ResultReg) + .addReg(SrcReg0, getKillRegState(Src0IsKill)) + .addReg(SrcReg1, getKillRegState(Src1IsKill)) + .addReg(VR); + // Insert the MADD + InsInstrs.push_back(MIB); + return MUL; +} + +/// genAlternativeCodeSequence - when hasPattern() finds a pattern +/// this function generates the instructions that could replace the +/// original code sequence +void AArch64InstrInfo::genAlternativeCodeSequence( + MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern, + SmallVectorImpl &InsInstrs, + SmallVectorImpl &DelInstrs, + DenseMap &InstrIdxForVirtReg) const { + MachineBasicBlock &MBB = *Root.getParent(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + MachineFunction &MF = *MBB.getParent(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + + MachineInstr *MUL; + const TargetRegisterClass *RC; + unsigned Opc; + switch (Pattern) { + default: + // signal error. + break; + case MachineCombinerPattern::MC_MULADDW_OP1: + case MachineCombinerPattern::MC_MULADDX_OP1: + // MUL I=A,B,0 + // ADD R,I,C + // ==> MADD R,A,B,C + // --- Create(MADD); + if (Pattern == MachineCombinerPattern::MC_MULADDW_OP1) { + Opc = AArch64::MADDWrrr; + RC = &AArch64::GPR32RegClass; + } else { + Opc = AArch64::MADDXrrr; + RC = &AArch64::GPR64RegClass; + } + MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); + break; + case MachineCombinerPattern::MC_MULADDW_OP2: + case MachineCombinerPattern::MC_MULADDX_OP2: + // MUL I=A,B,0 + // ADD R,C,I + // ==> MADD R,A,B,C + // --- Create(MADD); + if (Pattern == MachineCombinerPattern::MC_MULADDW_OP2) { + Opc = AArch64::MADDWrrr; + RC = &AArch64::GPR32RegClass; + } else { + Opc = AArch64::MADDXrrr; + RC = &AArch64::GPR64RegClass; + } + MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); + break; + case MachineCombinerPattern::MC_MULADDWI_OP1: + case MachineCombinerPattern::MC_MULADDXI_OP1: { + // MUL I=A,B,0 + // ADD R,I,Imm + // ==> ORR V, ZR, Imm + // ==> MADD R,A,B,V + // --- Create(MADD); + const TargetRegisterClass *OrrRC; + unsigned BitSize, OrrOpc, ZeroReg; + if (Pattern == MachineCombinerPattern::MC_MULADDWI_OP1) { + OrrOpc = AArch64::ORRWri; + OrrRC = &AArch64::GPR32spRegClass; + BitSize = 32; + ZeroReg = AArch64::WZR; + Opc = AArch64::MADDWrrr; + RC = &AArch64::GPR32RegClass; + } else { + OrrOpc = AArch64::ORRXri; + OrrRC = &AArch64::GPR64spRegClass; + BitSize = 64; + ZeroReg = AArch64::XZR; + Opc = AArch64::MADDXrrr; + RC = &AArch64::GPR64RegClass; + } + unsigned NewVR = MRI.createVirtualRegister(OrrRC); + uint64_t Imm = Root.getOperand(2).getImm(); + + if (Root.getOperand(3).isImm()) { + unsigned Val = Root.getOperand(3).getImm(); + Imm = Imm << Val; + } + uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize); + uint64_t Encoding; + if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) { + MachineInstrBuilder MIB1 = + BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR) + .addReg(ZeroReg) + .addImm(Encoding); + InsInstrs.push_back(MIB1); + InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); + MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); + } + break; + } + case MachineCombinerPattern::MC_MULSUBW_OP1: + case MachineCombinerPattern::MC_MULSUBX_OP1: { + // MUL I=A,B,0 + // SUB R,I, C + // ==> SUB V, 0, C + // ==> MADD R,A,B,V // = -C + A*B + // --- Create(MADD); + const TargetRegisterClass *SubRC; + unsigned SubOpc, ZeroReg; + if (Pattern == MachineCombinerPattern::MC_MULSUBW_OP1) { + SubOpc = AArch64::SUBWrr; + SubRC = &AArch64::GPR32spRegClass; + ZeroReg = AArch64::WZR; + Opc = AArch64::MADDWrrr; + RC = &AArch64::GPR32RegClass; + } else { + SubOpc = AArch64::SUBXrr; + SubRC = &AArch64::GPR64spRegClass; + ZeroReg = AArch64::XZR; + Opc = AArch64::MADDXrrr; + RC = &AArch64::GPR64RegClass; + } + unsigned NewVR = MRI.createVirtualRegister(SubRC); + // SUB NewVR, 0, C + MachineInstrBuilder MIB1 = + BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR) + .addReg(ZeroReg) + .addOperand(Root.getOperand(2)); + InsInstrs.push_back(MIB1); + InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); + MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); + break; + } + case MachineCombinerPattern::MC_MULSUBW_OP2: + case MachineCombinerPattern::MC_MULSUBX_OP2: + // MUL I=A,B,0 + // SUB R,C,I + // ==> MSUB R,A,B,C (computes C - A*B) + // --- Create(MSUB); + if (Pattern == MachineCombinerPattern::MC_MULSUBW_OP2) { + Opc = AArch64::MSUBWrrr; + RC = &AArch64::GPR32RegClass; + } else { + Opc = AArch64::MSUBXrrr; + RC = &AArch64::GPR64RegClass; + } + MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); + break; + case MachineCombinerPattern::MC_MULSUBWI_OP1: + case MachineCombinerPattern::MC_MULSUBXI_OP1: { + // MUL I=A,B,0 + // SUB R,I, Imm + // ==> ORR V, ZR, -Imm + // ==> MADD R,A,B,V // = -Imm + A*B + // --- Create(MADD); + const TargetRegisterClass *OrrRC; + unsigned BitSize, OrrOpc, ZeroReg; + if (Pattern == MachineCombinerPattern::MC_MULSUBWI_OP1) { + OrrOpc = AArch64::ORRWri; + OrrRC = &AArch64::GPR32spRegClass; + BitSize = 32; + ZeroReg = AArch64::WZR; + Opc = AArch64::MADDWrrr; + RC = &AArch64::GPR32RegClass; + } else { + OrrOpc = AArch64::ORRXri; + OrrRC = &AArch64::GPR64spRegClass; + BitSize = 64; + ZeroReg = AArch64::XZR; + Opc = AArch64::MADDXrrr; + RC = &AArch64::GPR64RegClass; + } + unsigned NewVR = MRI.createVirtualRegister(OrrRC); + int Imm = Root.getOperand(2).getImm(); + if (Root.getOperand(3).isImm()) { + unsigned Val = Root.getOperand(3).getImm(); + Imm = Imm << Val; + } + uint64_t UImm = -Imm << (64 - BitSize) >> (64 - BitSize); + uint64_t Encoding; + if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) { + MachineInstrBuilder MIB1 = + BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR) + .addReg(ZeroReg) + .addImm(Encoding); + InsInstrs.push_back(MIB1); + InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); + MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); + } + break; + } + } // end switch (Pattern) + // Record MUL and ADD/SUB for deletion + DelInstrs.push_back(MUL); + DelInstrs.push_back(&Root); + + return; +} + +/// \brief Replace csincr-branch sequence by simple conditional branch +/// +/// Examples: +/// 1. +/// csinc w9, wzr, wzr, +/// tbnz w9, #0, 0x44 +/// to +/// b. +/// +/// 2. +/// csinc w9, wzr, wzr, +/// tbz w9, #0, 0x44 +/// to +/// b. +/// +/// \param MI Conditional Branch +/// \return True when the simple conditional branch is generated +/// +bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const { + bool IsNegativeBranch = false; + bool IsTestAndBranch = false; + unsigned TargetBBInMI = 0; + switch (MI->getOpcode()) { + default: + llvm_unreachable("Unknown branch instruction?"); + case AArch64::Bcc: + return false; + case AArch64::CBZW: + case AArch64::CBZX: + TargetBBInMI = 1; + break; + case AArch64::CBNZW: + case AArch64::CBNZX: + TargetBBInMI = 1; + IsNegativeBranch = true; + break; + case AArch64::TBZW: + case AArch64::TBZX: + TargetBBInMI = 2; + IsTestAndBranch = true; + break; + case AArch64::TBNZW: + case AArch64::TBNZX: + TargetBBInMI = 2; + IsNegativeBranch = true; + IsTestAndBranch = true; + break; + } + // So we increment a zero register and test for bits other + // than bit 0? Conservatively bail out in case the verifier + // missed this case. + if (IsTestAndBranch && MI->getOperand(1).getImm()) + return false; + + // Find Definition. + assert(MI->getParent() && "Incomplete machine instruciton\n"); + MachineBasicBlock *MBB = MI->getParent(); + MachineFunction *MF = MBB->getParent(); + MachineRegisterInfo *MRI = &MF->getRegInfo(); + unsigned VReg = MI->getOperand(0).getReg(); + if (!TargetRegisterInfo::isVirtualRegister(VReg)) + return false; + + MachineInstr *DefMI = MRI->getVRegDef(VReg); + + // Look for CSINC + if (!(DefMI->getOpcode() == AArch64::CSINCWr && + DefMI->getOperand(1).getReg() == AArch64::WZR && + DefMI->getOperand(2).getReg() == AArch64::WZR) && + !(DefMI->getOpcode() == AArch64::CSINCXr && + DefMI->getOperand(1).getReg() == AArch64::XZR && + DefMI->getOperand(2).getReg() == AArch64::XZR)) + return false; + + if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) + return false; + + AArch64CC::CondCode CC = + (AArch64CC::CondCode)DefMI->getOperand(3).getImm(); + bool CheckOnlyCCWrites = true; + // Convert only when the condition code is not modified between + // the CSINC and the branch. The CC may be used by other + // instructions in between. + if (modifiesConditionCode(DefMI, MI, CheckOnlyCCWrites, &getRegisterInfo())) + return false; + MachineBasicBlock &RefToMBB = *MBB; + MachineBasicBlock *TBB = MI->getOperand(TargetBBInMI).getMBB(); + DebugLoc DL = MI->getDebugLoc(); + if (IsNegativeBranch) + CC = AArch64CC::getInvertedCondCode(CC); + BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB); + MI->eraseFromParent(); + return true; +}